linux-kernel - Re: [RFC 0/2] PCI: Introduce MSI chip infrastructure

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Date:	Sun, 24 Mar 2013 12:06:49 +0100
From:	Thomas Petazzoni <thomas.petazzoni@...e-electrons.com>
To:	Andrew Murray <andrew.murray@....com>
Cc:	Thierry Reding <thierry.reding@...onic-design.de>,
	Bjorn Helgaas <bhelgaas@...gle.com>,
	Arnd Bergmann <arnd@...db.de>,
	"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [RFC 0/2] PCI: Introduce MSI chip infrastructure

Andrew, Thierry,

On Fri, 22 Mar 2013 09:30:27 +0000, Andrew Murray wrote:

> I think this could work well. In the future if the use of an independent MSI
> controller is required, then new DT bindings for host-bridges could use
> phandles to reference independent MSI controllers as their providers of
> MSIs. I guess this functionality can be built on top of what you have proposed
> later as the need arises.

On Marvell HW (at least Armada 370/XP), MSIs are handled by the
main interrupt controller directly, or more precisely, managing the
MSIs requires fiddling with registers that are part of the interrupt
controller registers, and not part of the PCIe controller registers.

Basically, when a MSI interrupt is raised, it corresponds to IRQ 1 on
the main interrupt controller. Then, one has to read a register of the
main interrupt controller to find out which MSI interrupt was actually
triggered. So in our case, the MSI irq_chip really belongs to the
interrupt controller driver, and not the PCIe driver. Also, the
physical address to be added in the 'struct msi_msg' is the physical
address of an interrupt controller register.

Therefore, I'm not sure how to do the interaction between the PCIe
driver and the interrupt controller driver.

Suggestions?

I'll try to post some ugly code next week just to show what is
happening.

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
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