linux-kernel - Re: perf: forcing instructions event to run on Fixed Counter 0

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Date:	Mon, 15 Apr 2013 12:39:05 -0400 (EDT)
From:	Vince Weaver <vincent.weaver@...ne.edu>
To:	eranian@...il.com
cc:	linux-kernel@...r.kernel.org,
	Peter Zijlstra <a.p.zijlstra@...llo.nl>,
	Paul Mackerras <paulus@...ba.org>,
	Ingo Molnar <mingo@...hat.com>,
	Arnaldo Carvalho de Melo <acme@...stprotocols.net>
Subject: Re: perf: forcing instructions event to run on Fixed Counter 0

On Mon, 15 Apr 2013, Stephane Eranian wrote:

> Never heard of that problem. I know there was another problem due to leaking
> during priv level transitions. It would be take a few instr or cycles to realize
> you were not in user level any more when doing event:u.
> 
> Interrupt should impact fixed and generic counters the same way.

Some people inside Intel were reproducing my "deterministic event" work 
and they informed me of this issue.

> Are you sure that the 5th event stayed in fixed counter 0 all along?

No, but is there any way to enforce that currently using perf?

The results are about what I'd expect.  The generic instructions:u
events are overcounting by roughly 20,008 for page faults (as expected)
and 650 for hardware interrupts (also as expected) wheras the 
Fixed Counter 0 event is overcounting 10,000 (for page faults?) and 
undercounting a bit possibly due to a supposedly known issue involving
the counts for rep-prefixed string instructions that apparently only 
happens on Fixed Counter 0.
 
> > $ perf stat -e instructions:u,instructions:u,instructions:u,instructions:u,instructions:u ./retired_instr.all.x86_64
> > ...
> >  Performance counter stats for './retired_instr.all.x86_64':
> >
> >        227,010,687 instructions:u            #    0.00  insns per cycle
> >        227,010,687 instructions:u            #    0.00  insns per cycle
> >        227,010,687 instructions:u            #    0.00  insns per cycle
> >        227,010,687 instructions:u            #    0.00  insns per cycle
> >        227,000,723 instructions:u            #    0.00  insns per cycle
> >
> >        1.902648316 seconds time elapsed


Vince Weaver
vincent.weaver@...ne.edu
http://www.eece.maine.edu/~vweaver/
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