linux-kernel - Re: [PATCH 1/2] GPIO: Add support for dual channel in gpio-xilinx.c

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Date:	Fri, 31 May 2013 09:34:57 +0200
From:	Michal Simek <monstr@...str.eu>
To:	Linus Walleij <linus.walleij@...aro.org>
CC:	Michal Simek <michal.simek@...inx.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Grant Likely <grant.likely@...aro.org>,
	Rob Herring <rob.herring@...xeda.com>,
	"devicetree-discuss@...ts.ozlabs.org" 
	<devicetree-discuss@...ts.ozlabs.org>
Subject: Re: [PATCH 1/2] GPIO: Add support for dual channel in gpio-xilinx.c

On 05/31/2013 09:14 AM, Linus Walleij wrote:
> On Fri, May 31, 2013 at 7:43 AM, Michal Simek <monstr@...str.eu> wrote:
>> On 05/30/2013 09:46 PM, Linus Walleij wrote:
> 
>>> (...)
>>>> +/* Read/Write access to the GPIO registers */
>>>> +#define xgpio_readreg(offset)          __raw_readl(offset)
>>>> +#define xgpio_writereg(offset, val)    __raw_writel(val, offset)
>>>
>>> So you're swithing in_be32/out_be32 to the CPU-dependent
>>> __raw_readl/__raw_writel functions? Why?
>>
>> The reason is that this driver can be used on ARM where in_be32/out_be32
>> is not implemented.
> 
> OK I buy this (and the following explanation).
> 
> I think readl/writel is always in LE (PCI) endianness anyway, which
> is likely not what you want. (I suspect the next point was about
> that.)

readl/writel yes it is all the time little endian
but __raw_readl/__raw_writel is just *(u32 *)ptr access
without any endian checking and barriers.

Probably the best way how to handle is to write
#ifdef ARCH_ZYNQ
# define xgpio_readreg(offset)          readl(offset)
# define xgpio_writereg(offset, val)    writel(val, offset)
#else
# define xgpio_readreg(offset)          __raw_readl(offset)
# define xgpio_writereg(offset, val)    __raw_writel(val, offset)
#endif

But still it is not correct in sense that I shouldn't pretend
that __raw_readl is ok to run on ppc and microblaze big endian.
But using another ifdef BIG_ENDIAN or ARCH don't improve it.

If there is one more register which I can use for autodetection,
it will be easy to choose but that's not this case.

>>> Have you documented these new bindings? It doesn't seem so.
>>> Documentation/devicetree/bindings/gpio/*...
>>>
>>> If it's undocumented so far, this is a good oppotunity to add it.
>>
>> Isn't it enough what it is in 2/2?
> 
> I didn't see 2/2, I guess I wasn't on CC...
> 
> Anyway I guess it's this:
> http://marc.info/?l=linux-kernel&m=136982686732560&w=2

Yes. it is. I am using patman and you are probably not listed
in MAINTAINERS for this folder to automatically add you.
Will add you manually.

> It's OK, but fix the boolean member so as to just needing to
> be present:
> 
> xlnx,is-dual;
> 
> Rather than
> 
> xlnx,is-dual = <1>;

Surely I can do it but it means to change our BSP and because
this IP is used on Microblaze from beginning this change
breaks all DTSes from past.
That's why I would prefer not to change logic here because
it just breaks all Microblaze DTSes which were generated
till this change (All of them contains xlnx,is-dual = <0>
if dual channel is not used).

I will definitely look at dt function in the whole driver
and use the

>> Or do you want to describe current binding in the first patch
>> and then extend it in this patch when dual channel is added?
> 
> Nah. 2/2 is fine.

ok.

>>> This is basically a jam table (hardware set-up) in the device tree.
>>
>> Not sure what you mean by that. Xilinx GPIO is soft IP which can be configured
>> to different configurations before bitstream is generated.
>> At the end you will get different setting/addresses setup for every pin
>> which is described by these xlnx,X descriptions.
>>
>>> I don't exactly like this. Is this necessary?
>>
>> If you mean names or values in there that all of them are autogenerated
>> from design tools and they are reflect IP hardware description and all
>> configuration options which you can have there.
>> It means that all these values give you exact hardware description.
>>
>> Do I answer your question?
> 
> Yes, this is OK, I buy that explanation. I thought it was
> something else.

ok

> I think the overall problem is that I do not understand what a
> "channel" is in this context, and thus it is hard to understand the
> patch as a whole. 2/2 could add some more verbose explanation
> about the HW IP so I get comfortable and can understand the
> whole hardware block...

ok. Good.

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform



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