linux-kernel - Re: [PATCH 4/4] Documentation: Add device tree bindings for Freescale FTM PWM

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:	Fri, 30 Aug 2013 14:11:56 -0600
From:	Stephen Warren <swarren@...dotorg.org>
To:	Kumar Gala <galak@...nel.crashing.org>
CC:	Xiubo Li <Li.Xiubo@...escale.com>, r65073@...escale.com,
	thierry.reding@...il.com, grant.likely@...aro.org,
	linux@....linux.org.uk, rob@...dley.net, ian.campbell@...rix.com,
	mark.rutland@....com, pawel.moll@....com, rob.herring@...xeda.com,
	linux-arm-kernel@...ts.infradead.org, linux-pwm@...r.kernel.org,
	linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
	linux-doc@...r.kernel.org
Subject: Re: [PATCH 4/4] Documentation: Add device tree bindings for Freescale
 FTM PWM

On 08/30/2013 01:19 PM, Kumar Gala wrote:
> Should have at least something w/regards to a commit message.
> 
> On Aug 20, 2013, at 10:07 PM, Xiubo Li wrote:
> 
>> Signed-off-by: Xiubo Li <Li.Xiubo@...escale.com>
>> ---
>> .../devicetree/bindings/pwm/fsl-ftm-pwm.txt        | 52 ++++++++++++++++++++++
>> 1 file changed, 52 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pwm/fsl-ftm-pwm.txt
>>
>> diff --git a/Documentation/devicetree/bindings/pwm/fsl-ftm-pwm.txt b/Documentation/devicetree/bindings/pwm/fsl-ftm-pwm.txt
>> new file mode 100644
>> index 0000000..698965b
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pwm/fsl-ftm-pwm.txt
>> @@ -0,0 +1,52 @@
>> +Freescale FTM PWM controller
>> +
>> +Required properties:
>> +- compatible: should be "fsl,vf610-ftm-pwm"
>> +- reg: physical base address and length of the controller's registers
>> +- #pwm-cells: Should be 3. Number of cells being used to specify PWM property.
>> +  First cell specifies the per-chip channel index of the PWM to use, the
>> +  second cell is the period in nanoseconds and bit 0 in the third cell is
>> +  used to encode the polarity of PWM output. Set bit 0 of the third in PWM
>> +  specifier to 1 for inverse polarity & set to 0 for normal polarity.
>> +- fsl,pwm-clk-ps: the ftm0 pwm clock's prescaler, divide-by 2^n(n = 0 ~ 7).
>> +- fsl,pwm-cpwm: Center-Aligned PWM (CPWM) mode.
> 
> Should describe this in more detail, what does the value actually mean for what modes there are?

Assuming "CPWM" is clearly explained in the HW documentation for this
chip (I have no idea if that's actually the case), then is it still
necessary to explain what this means in *detail*? Perhaps simply "see
section XXX in the TRM" or "see register XXX, bit YYY in the HW
documentation" would be enough?
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/