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Date:	Thu, 26 Sep 2013 12:45:48 +0200
From:	Alexander Gordeev <agordeev@...hat.com>
To:	David Laight <David.Laight@...LAB.COM>
Cc:	Tejun Heo <tj@...nel.org>, linux-pci@...r.kernel.org,
	Joerg Roedel <joro@...tes.org>, x86@...nel.org,
	linux-kernel@...r.kernel.org, linux-ide@...r.kernel.org,
	Jan Beulich <JBeulich@...e.com>,
	Bjorn Helgaas <bhelgaas@...gle.com>,
	linuxppc-dev@...ts.ozlabs.org, Ingo Molnar <mingo@...nel.org>
Subject: Re: [PATCH v2 2/6] PCI/MSI: Factor out pci_get_msi_cap() interface

On Thu, Sep 26, 2013 at 09:58:53AM +0100, David Laight wrote:
> Would it be possible to do some kind of 2-stage allocation.
> In the first pass the driver would pass a minimum and desired
> number of MSI-X interrupts, but not actually be given any.

Repeated calls to msi_enable_msi/msix() is what we are trying to avoid.

> Interrupts could then be allocated after it is known how many
> are required and how many are available.

Yep, that what we are heading to. So basic pattern I see would be like this:

	int foo_driver_enable_msix(struct pci_dev *pdev, int nvec)
	{
		...

		rc = pci_msix_table_size(pdev);
		if (rc < 0)
			return rc;

		nvec = min(nvec, rc);
		if (nvec < FOO_DRIVER_MINIMUM_NVEC)
			goto single_msi;

		for (i = 0; i < nvec; i++)
			entries[i].entry = i;

		rc = pci_enable_msix(pdev, entries, nvec);
		if (rc)
			goto single_msi;

		return 0;

	single_msi:
		...

	}

But this will break pSeries and we might end up with something like this:

	int foo_driver_enable_msix(struct pci_dev *pdev, int nvec)
	{
		...

		rc = pci_msix_table_size(pdev);
		if (rc < 0)
			return rc;

		nvec = min(nvec, rc);
		if (nvec < FOO_DRIVER_MINIMUM_NVEC)
			goto single_msi;

		rc = pci_get_msix_limit(pdev, nvec);
		if (rc < 0)
			return rc;

		nvec = min(nvec, rc);
		if (nvec < FOO_DRIVER_MINIMUM_NVEC)
			goto single_msi;

		for (i = 0; i < nvec; i++)
			entries[i].entry = i;

		rc = pci_enable_msix(pdev, entries, nvec);
		if (rc)
			goto single_msi;

		return 0;

	single_msi:
		...

	}

> 	David

-- 
Regards,
Alexander Gordeev
agordeev@...hat.com
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