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Date: Mon, 28 Oct 2013 12:54:57 +0530 From: Mj Embd <mj.embd@...il.com> To: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, linaro-kernel <linaro-kernel@...ts.linaro.org>, Simon Glass <sjg@...omium.org> Subject: ARM GIC Virtualization question Hi All, a) As per GIC-400 all Physical interrupts trap into hypervisor b) Hypervisor does ACK, programs Virtual GIC list registers (with PhysIRQ:VIRQ) and does a world switch. c) GIC CPU I/f interrupts Guest with the VIRQ d) Guest does a ACK and EOI to GIC cpu i/f e) Hypervisor gets a maintenance interrupt when Guest Does an EOI f) Hypervisor then clears the Physical Interrupt So for 1 interrupt there are so many context switches ? Is the sequence right. If I am missing anything please let me know .. Also, If a device is private to a guest, so many context switches would reduce the performance if the device interrupts a lot. My question is that a) Is the above flow correct ? b) Is this the only flow or there exists some optimisations Thanks and Regards -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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