linux-kernel - Re: [PATCH] arm: mm: add memory type for inner-writeback

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:	Tue, 7 Jan 2014 15:09:21 +0000
From:	Catalin Marinas <catalin.marinas@....com>
To:	Mark Zhang <markz@...dia.com>
Cc:	"linux@....linux.org.uk" <linux@....linux.org.uk>,
	"steve.capper@...aro.org" <steve.capper@...aro.org>,
	"nico@...aro.org" <nico@...aro.org>,
	"ccross@...roid.com" <ccross@...roid.com>,
	Will Deacon <Will.Deacon@....com>,
	"lauraa@...eaurora.org" <lauraa@...eaurora.org>,
	"akpm@...ux-foundation.org" <akpm@...ux-foundation.org>,
	"christoffer.dall@...aro.org" <christoffer.dall@...aro.org>,
	"viro@...iv.linux.org.uk" <viro@...iv.linux.org.uk>,
	"gregory.clement@...e-electrons.com" 
	<gregory.clement@...e-electrons.com>,
	"ben-linux@...ff.org" <ben-linux@...ff.org>,
	"paul.gortmaker@...driver.com" <paul.gortmaker@...driver.com>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Gary King <gking@...dia.com>
Subject: Re: [PATCH] arm: mm: add memory type for inner-writeback

On Fri, Dec 27, 2013 at 04:58:48AM +0000, Mark Zhang wrote:
> From: Colin Cross <ccross@...roid.com>
> 
> For streaming-style operations (e.g., software rendering of graphics
> surfaces shared with non-coherent DMA devices), the cost of performing
> L2 cache maintenance can exceed the benefit of having the larger cache
> (this is particularly true for OUTER_CACHE configurations like the ARM
> PL2x0).
> 
> This change uses the currently-unused mapping 5 (TEX[0]=1, C=0, B=1)
> in the tex remapping tables as an inner-writeback-write-allocate, outer
> non-cacheable memory type, so that this mapping will be available to
> clients which will benefit from the reduced L2 maintenance.
> 
> Signed-off-by: Gary King <gking@...dia.com>

Is Colin signing off this patch as well?

> --- a/arch/arm/mm/proc-v7-2level.S
> +++ b/arch/arm/mm/proc-v7-2level.S
> @@ -144,8 +144,8 @@ ENDPROC(cpu_v7_set_pte_ext)
>  	 *   NS1 = PRRR[19] = 1		- normal shareable property
>  	 *   NOS = PRRR[24+n] = 1	- not outer shareable
>  	 */
> -.equ	PRRR,	0xff0a81a8
> -.equ	NMRR,	0x40e040e0
> +.equ	PRRR,	0xff0a89a8
> +.equ	NMRR,	0x40e044e0

It should be done for the *-3level files.

-- 
Catalin
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/