lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:	Fri, 04 Apr 2014 13:56:54 -0500
From:	Alex Elder <elder@...aro.org>
To:	Tim Kryger <tim.kryger@...aro.org>
CC:	Matt Porter <mporter@...aro.org>,
	Christian Daudt <bcm@...thebug.org>,
	Device Tree List <devicetree@...r.kernel.org>,
	Arnd Bergmann <arnd@...db.de>, sboyd@...eaurora.org,
	Broadcom Kernel Feedback List 
	<bcm-kernel-feedback-list@...adcom.com>,
	ARM Kernel List <linux-arm-kernel@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 2/5] ARM: add SMP support for Broadcom mobile SoCs

On 04/04/2014 10:30 AM, Tim Kryger wrote:
> On Thu, Apr 3, 2014 at 7:18 PM, Alex Elder <elder@...aro.org> wrote:
> 
>> diff --git a/arch/arm/mach-bcm/platsmp.c b/arch/arm/mach-bcm/platsmp.c
>> new file mode 100644
>> index 0000000..46a64f2
>> --- /dev/null
>> +++ b/arch/arm/mach-bcm/platsmp.c
> 
>> +/* Size of mapped Cortex A9 SCU address space */
>> +#define SCU_SIZE               0x58
> 
>> +/*
>> + * Enable the Cortex A9 Snoop Control Unit
>> + *
>> + * By the time this is called we already know there are multiple
>> + * cores present.  We assume we're running on a Cortex A9 processor,
>> + * so any trouble getting the base address register or getting the
>> + * SCU base is a problem.
>> + *
>> + * Return 0 if successful or an error code otherwise.
>> + */
>> +static int __init scu_a9_enable(void)
>> +{
>> +       unsigned long config_base;
>> +       void __iomem *scu_base;
>> +
>> +       if (!scu_a9_has_base()) {
>> +               pr_err("no configuration base address register!\n");
>> +               return -ENXIO;
>> +       }
>> +
>> +       /* Config base address register value is zero for uniprocessor */
>> +       config_base = scu_a9_get_base();
>> +       if (!config_base) {
>> +               pr_err("hardware reports only one core; disabling SMP\n");
>> +               return -ENOENT;
>> +       }
>> +
>> +       scu_base = ioremap((phys_addr_t)config_base, SCU_SIZE);
>> +       if (!scu_base) {
>> +               pr_err("failed to remap config base (%lu/%u) for SCU\n",
>> +                       config_base, SCU_SIZE);
>> +               return -ENOMEM;
>> +       }
>> +
>> +       scu_enable(scu_base);
>> +
>> +       iounmap(scu_base);      /* That's the last we'll need of this */
>> +
>> +       return 0;
>> +}
> 
> This function seems useful for Cortex A9 MPCore in general.
> 
> While you gave it a generic name, you put it in a Broadcom file.
> 
> Is there a better location for this code?

I think it belongs in arch/arm/kernel/smp_scu.c.  I was thinking
it might be generally useful when I wrote it (hence the more
complete header comment, for example).  And I'll gladly move
it there, I just didn't want anybody to get hung up on that.

					-Alex


--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ