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Date:	Tue, 15 Apr 2014 10:39:24 +0530
From:	Vivek Gautam <gautam.vivek@...sung.com>
To:	Sylwester Nawrocki <s.nawrocki@...sung.com>
Cc:	Linux USB Mailing List <linux-usb@...r.kernel.org>,
	"linux-samsung-soc@...r.kernel.org" 
	<linux-samsung-soc@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	linux-doc@...r.kernel.org, kishon <kishon@...com>,
	Greg KH <gregkh@...uxfoundation.org>,
	Felipe Balbi <balbi@...com>,
	Kukjin Kim <kgene.kim@...sung.com>,
	Tomasz Figa <t.figa@...sung.com>,
	Kamil Debski <k.debski@...sung.com>,
	Jingoo Han <jg1.han@...sung.com>
Subject: Re: [PATCH V4 1/5] phy: Add new Exynos5 USB 3.0 PHY driver

Hi,


On Mon, Apr 14, 2014 at 8:07 PM, Sylwester Nawrocki
<s.nawrocki@...sung.com> wrote:
> On 08/04/14 16:36, Vivek Gautam wrote:
>> diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
>> index 28f9edb..6d99ba9 100644
>> --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
>> +++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
>> @@ -74,3 +74,45 @@ phy-consumer@...40000 {
>>
>>  Refer to DT bindings documentation of particular PHY consumer devices for more
>>  information about required PHYs and the way of specification.
>> +
>> +Samsung Exynos5 SoC series USB DRD PHY controller
>> +--------------------------------------------------
>> +
>> +Required properties:
>> +- compatible : Should be set to one of the following supported values:
>> +     - "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC,
>> +     - "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC.
>> +- reg : Register offset and length of USB DRD PHY register set;
>> +- clocks: Clock IDs array as required by the controller
>> +- clock-names: names of clocks correseponding to IDs in the clock property;
>> +            Required clocks:
>> +     - phy: main PHY clock (same as USB DRD controller i.e. DWC3 IP clock),
>> +            used for register access.
>> +     - ref: PHY's reference clock (usually crystal clock), associated by
>> +            phy name, used to determine bit values for clock settings
>> +            register.
>> +     Additional clock required for Exynos5420:
>> +     - usb30_sclk_100m: Additional special clock used for PHY operation
>> +                        depicted as 'sclk_usbphy30' in CMU of Exynos5420.
>> +- samsung,syscon-phandle: phandle for syscon interface, which is used to
>> +                       control pmu registers for power isolation.
>
> Why to append "-phandle" to the property's name ? If this is for PMU
> perhaps make it more explicit and name it: samsung,pmu-syscon or
> samsung,pmureg ?

Right, thanks for pointing out this.
Will rename it to samsung,pmu-syscon. That will be inline with the
phandle it points to.
--
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