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Date:	Tue, 29 Apr 2014 12:20:13 +0200
From:	Borislav Petkov <bp@...e.de>
To:	Andreas Herrmann <herrmann.der.user@...glemail.com>,
	Suravee Suthikulpanit <suravee.suthikulpanit@....com>
Cc:	Bjorn Helgaas <bhelgaas@...gle.com>,
	Robert Richter <rric@...nel.org>,
	Myron Stowe <myron.stowe@...il.com>,
	Myron Stowe <myron.stowe@...hat.com>,
	Aravind Gopalakrishnan <aravind.gopalakrishnan@....com>,
	linux-pci <linux-pci@...r.kernel.org>, kim.naru@....com,
	Daniel J Blueman <daniel@...ascale.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Ingo Molnar <mingo@...hat.com>,
	"H. Peter Anvin" <hpa@...or.com>, x86 <x86@...nel.org>,
	Steffen Persvold <sp@...ascale.com>,
	"linux-acpi@...r.kernel.org" <linux-acpi@...r.kernel.org>,
	LKML <linux-kernel@...r.kernel.org>,
	Jan Beulich <JBeulich@...e.com>,
	Yinghai Lu <yinghai@...nel.org>
Subject: Re: [PATCH v2 2/5] x86/PCI: Support additional MMIO range
 capabilities

On Tue, Apr 29, 2014 at 09:33:09AM +0200, Andreas Herrmann wrote:
> I am sure, it's because some server systems had MMIO ECS access not
> enabled in BIOS. I can't remember which systems were affected.

Ok, now AMD people: what's the story with IO ECS, can we assume that on
everything after F10h, BIOS has a sensible MCFG and we can limit this to
F10h only? I like Bjorn's idea but we need to make sure a working MCFG
is ubiquitous.

Which begs the real question: Suravee, why are you even touching IO ECS
provided F15h and later have a MCFG? Or, do they?

-- 
Regards/Gruss,
    Boris.

Sent from a fat crate under my desk. Formatting is fine.
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