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Date:	Wed, 28 May 2014 10:09:12 +0530
From:	Preeti U Murthy <preeti@...ux.vnet.ibm.com>
To:	benh@...nel.crashing.org, linux-kernel@...r.kernel.org,
	svaidyan@...ibm.com, paulus@...ba.org,
	srivatsa.bhat@...ux.vnet.ibm.com, linuxppc-dev@...ts.ozlabs.org
Subject: [PATCH 4/6] KVM: PPC: Book3S HV: Consolidate the idle-state enter
 sequence in KVM

From: Srivatsa S. Bhat <srivatsa.bhat@...ux.vnet.ibm.com>

Now that the support for fast sleep idle state is present, the KVM
standby threads can be put to fast sleep when they are either idle
or do not have a guest to run. Today they enter nap in these scenarios.
The purpose is to gain maximum power savings in a KVM scenario as well
when an entire cpu core is idle.

As a precursor, consolidate the code common across all idle states.

Signed-off-by: Srivatsa S. Bhat <srivatsa.bhat@...ux.vnet.ibm.com>
[ Changelog added by <preeti@...ux.vnet.ibm.com> ]
Signed-off-by: Preeti U Murthy <preeti@...ux.vnet.ibm.com>
---

 arch/powerpc/kvm/book3s_hv_rmhandlers.S |   30 ++++++++++++++++--------------
 1 file changed, 16 insertions(+), 14 deletions(-)

diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
index b031f93..43aa806 100644
--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -40,6 +40,17 @@
 #define NAPPING_CEDE	1
 #define NAPPING_NOVCPU	2
 
+#define IDLE_STATE_ENTER_SEQ_HV(IDLE_INST)			\
+	/* Magic NAP/SLEEP/WINKLE mode enter sequence */	\
+	std	r0, HSTATE_SCRATCH0(r13);			\
+	ptesync;						\
+	ld	r0, HSTATE_SCRATCH0(r13);			\
+1:	cmpd	r0, r0;						\
+	bne	1b;						\
+	IDLE_INST;						\
+	b	.
+
+
 /*
  * Call kvmppc_hv_entry in real mode.
  * Must be called with interrupts hard-disabled.
@@ -325,13 +336,9 @@ kvm_do_nap:
 	rlwimi	r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
 	mtspr	SPRN_LPCR, r4
 	isync
-	std	r0, HSTATE_SCRATCH0(r13)
-	ptesync
-	ld	r0, HSTATE_SCRATCH0(r13)
-1:	cmpd	r0, r0
-	bne	1b
-	nap
-	b	.
+	IDLE_STATE_ENTER_SEQ_HV(PPC_NAP)
+	/* No return */
+
 
 /******************************************************************************
  *                                                                            *
@@ -2027,13 +2034,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
 	mtspr	SPRN_LPCR,r5
 	isync
 	li	r0, 0
-	std	r0, HSTATE_SCRATCH0(r13)
-	ptesync
-	ld	r0, HSTATE_SCRATCH0(r13)
-1:	cmpd	r0, r0
-	bne	1b
-	nap
-	b	.
+	IDLE_STATE_ENTER_SEQ_HV(PPC_NAP)
+	/* No return */
 
 33:	mr	r4, r3
 	li	r3, 0

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