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Date: Mon, 7 Jul 2014 12:53:48 -0400
From: Murali Karicheri <m-karicheri2@...com>
To: Mohit KUMAR DCG <Mohit.KUMAR@...com>
CC: "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
Santosh Shilimkar <santosh.shilimkar@...com>,
Russell King <linux@....linux.org.uk>,
Grant Likely <grant.likely@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Jingoo Han <jg1.han@...sung.com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Pratyush ANAND <pratyush.anand@...com>,
Richard Zhu <r65037@...escale.com>,
Kishon Vijay Abraham I <kishon@...com>,
Marek Vasut <marex@...x.de>, Arnd Bergmann <arnd@...db.de>,
Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>,
Randy Dunlap <rdunlap@...radead.org>
Subject: Re: [PATCH v3 1/5] PCI: designware: add rd[wr]_other_conf API
On 07/07/2014 12:11 AM, Mohit KUMAR DCG wrote:
> Hello Murali,
>
>> -----Original Message-----
>> From: Murali Karicheri [mailto:m-karicheri2@...com]
>> Sent: Tuesday, July 01, 2014 3:15 AM
>> To: linux-pci@...r.kernel.org; linux-kernel@...r.kernel.org;
>> devicetree@...r.kernel.org
>> Cc: Murali Karicheri; Santosh Shilimkar; Russell King; Grant Likely; Rob Herring;
>> Mohit KUMAR DCG; Jingoo Han; Bjorn Helgaas; Pratyush ANAND; Richard
>> Zhu; Kishon Vijay Abraham I; Marek Vasut; Arnd Bergmann; Pawel Moll;
>> Mark Rutland; Ian Campbell; Kumar Gala; Randy Dunlap
>> Subject: [PATCH v3 1/5] PCI: designware: add rd[wr]_other_conf API
>>
>> v3.65 version of the designware h/w, requires application space registers to
>> be configured to access the remote EP config space.
>> To support this, add rd[wr]_other_conf API in the pcie_host_opts
>>
>> Signed-off-by: Murali Karicheri<m-karicheri2@...com>
>>
>> CC: Santosh Shilimkar<santosh.shilimkar@...com>
>> CC: Russell King<linux@....linux.org.uk>
>> CC: Grant Likely<grant.likely@...aro.org>
>> CC: Rob Herring<robh+dt@...nel.org>
>> CC: Mohit Kumar<mohit.kumar@...com>
>> CC: Jingoo Han<jg1.han@...sung.com>
>> CC: Bjorn Helgaas<bhelgaas@...gle.com>
>> CC: Pratyush Anand<pratyush.anand@...com>
>> CC: Richard Zhu<r65037@...escale.com>
>> CC: Kishon Vijay Abraham I<kishon@...com>
>> CC: Marek Vasut<marex@...x.de>
>> CC: Arnd Bergmann<arnd@...db.de>
>> CC: Pawel Moll<pawel.moll@....com>
>> CC: Mark Rutland<mark.rutland@....com>
>> CC: Ian Campbell<ijc+devicetree@...lion.org.uk>
>> CC: Kumar Gala<galak@...eaurora.org>
>> CC: Randy Dunlap<rdunlap@...radead.org>
>> CC: Grant Likely<grant.likely@...aro.org>
>> ---
>> drivers/pci/host/pcie-designware.c | 12 ++++++++++--
>> drivers/pci/host/pcie-designware.h | 4 ++++
>> 2 files changed, 14 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-
>> designware.c
>> index 1eaf4df..d8f3af7 100644
>> --- a/drivers/pci/host/pcie-designware.c
>> +++ b/drivers/pci/host/pcie-designware.c
>> @@ -656,7 +656,11 @@ static int dw_pcie_rd_conf(struct pci_bus *bus, u32
>> devfn, int where,
>> }
>>
>> if (bus->number != pp->root_bus_nr)
>> - ret = dw_pcie_rd_other_conf(pp, bus, devfn,
>> + if (pp->ops->rd_other_conf)
>> + ret = pp->ops->rd_other_conf(pp, bus, devfn,
>> + where, size, val);
>> + else
>> + ret = dw_pcie_rd_other_conf(pp, bus, devfn,
>> where, size, val);
>> else
>> ret = dw_pcie_rd_own_conf(pp, where, size, val); @@ -
>> 679,7 +683,11 @@ static int dw_pcie_wr_conf(struct pci_bus *bus, u32
>> devfn,
>> return PCIBIOS_DEVICE_NOT_FOUND;
>>
>> if (bus->number != pp->root_bus_nr)
>> - ret = dw_pcie_wr_other_conf(pp, bus, devfn,
>> + if (pp->ops->wr_other_conf)
>> + ret = pp->ops->wr_other_conf(pp, bus, devfn,
>> + where, size, val);
>> + else
>> + ret = dw_pcie_wr_other_conf(pp, bus, devfn,
>> where, size, val);
>> else
>> ret = dw_pcie_wr_own_conf(pp, where, size, val); diff --git
>> a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
>> index 77f592f..8121901 100644
>> --- a/drivers/pci/host/pcie-designware.h
>> +++ b/drivers/pci/host/pcie-designware.h
>> @@ -61,6 +61,10 @@ struct pcie_host_ops {
>> u32 val, void __iomem *dbi_base);
>> int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32
>> *val);
>> int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32
>> val);
>> + int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
>> + unsigned int devfn, int where, int size, u32 *val);
>> + int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
>> + unsigned int devfn, int where, int size, u32 val);
>> int (*link_up)(struct pcie_port *pp);
>> void (*host_init)(struct pcie_port *pp); };
>
> - Now it looks good to me.
>
> Acked-by: Mohit Kumar<mohit.kumar@...com>
>
> Regards
> Mohit
>> --
>> 1.7.9.5
>
Mohit,
Thanks.
Jingoo, could you provide your response or Ack?
Thanks
Murali
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