linux-kernel - Re: [PATCH v2 12/29] nios2: Interrupt handling

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Date:	Fri, 18 Jul 2014 14:55:01 +0800
From:	Ley Foon Tan <lftan@...era.com>
To:	Thomas Gleixner <tglx@...utronix.de>
Cc:	Linux-Arch <linux-arch@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-doc@...r.kernel.org" <linux-doc@...r.kernel.org>,
	Chung-Lin Tang <cltang@...esourcery.com>
Subject: Re: [PATCH v2 12/29] nios2: Interrupt handling

On Thu, Jul 17, 2014 at 9:58 PM, Thomas Gleixner <tglx@...utronix.de> wrote:
> On Thu, 17 Jul 2014, Ley Foon Tan wrote:
>
>> On Tue, Jul 15, 2014 at 5:51 PM, Thomas Gleixner <tglx@...utronix.de> wrote:
>> > On Tue, 15 Jul 2014, Ley Foon Tan wrote:

>> >> +static void chip_unmask(struct irq_data *d)
>> >> +{
>> >> +     u32 ien;
>> >> +     ien = RDCTL(CTL_IENABLE);
>> >> +     ien |= (1 << d->hwirq);
>> >> +     WRCTL(CTL_IENABLE, ien);
>> >
>> > So this is UP only, right?
>> Yes, this is to enable one interrupt.
>
> The question was, whether this is always a UniProcessor machine.
Yes, it is UP.
>
>> > Also why don't you cache the register content so spare the extra read
>> > from the hardware?
>> Need to make sure nobody modify the register if we cache the register content.
>> Will keep as it is.
>
> Sigh.
>
> If this is a uniprocessor only design, then nothing can modify the
> cached values as all these functions are always called with interrupts
> disabled.
>
> If this should be SMP safe, then you'd need serialization of the
> register access as well becasue the read/modify/write sequence is not
> atomic.
Okay, we can cache the value.
Thanks.

Regards
Ley Foon
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