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Date:	Fri,  5 Sep 2014 10:32:13 +0800
From:	Addy Ke <addy.ke@...k-chips.com>
To:	wsa@...-dreams.de, max.schwarz@...ine.de, heiko@...ech.de,
	olof@...om.net, dianders@...omium.org
Cc:	linux-i2c@...r.kernel.org, linux-kernel@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org,
	linux-rockchip@...ts.infradead.org, cf@...k-chips.com,
	xjq@...k-chips.com, huangtao@...k-chips.com, zyw@...k-chips.com,
	yzq@...k-chips.com, hj@...k-chips.com, kever.yang@...k-chips.com,
	hl@...k-chips.com, caesar.wang@...k-chips.com,
	zhengsq@...k-chips.com, Addy Ke <addy.ke@...k-chips.com>
Subject: [PATCH] i2c: rk3x: fix divisor calculation for SCL frequency

I2C_CLKDIV register descripted in the previous version of
RK3x chip manual is incorrect. Plus 1 is required.

The correct formula:
- T(SCL_HIGH) = T(PCLK) * (CLKDIVH + 1) * 8
- T(SCL_LOW) = T(PCLK) * (CLKDIVL + 1) * 8
- (SCL Divsor) = 8 * ((CLKDIVL + 1) + (CLKDIVH + 1))
- SCL = PCLK / (CLK Divsor)

It will be updated to the latest version of chip manual.

Signed-off-by: Addy Ke <addy.ke@...k-chips.com>
---
 drivers/i2c/busses/i2c-rk3x.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c
index e637c32..76b6604 100644
--- a/drivers/i2c/busses/i2c-rk3x.c
+++ b/drivers/i2c/busses/i2c-rk3x.c
@@ -433,8 +433,8 @@ static void rk3x_i2c_set_scl_rate(struct rk3x_i2c *i2c, unsigned long scl_rate)
 	unsigned long i2c_rate = clk_get_rate(i2c->clk);
 	unsigned int div;
 
-	/* SCL rate = (clk rate) / (8 * DIV) */
-	div = DIV_ROUND_UP(i2c_rate, scl_rate * 8);
+	/* SCL rate = (clk rate) / (8 * (DIV + 2)) */
+	div = DIV_ROUND_UP(i2c_rate, scl_rate * 8) - 2;
 
 	/* The lower and upper half of the CLKDIV reg describe the length of
 	 * SCL low & high periods. */
-- 
1.8.3.2


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