linux-kernel - Re: [PATCH v2 7/8] phy: miphy28lp: Add SSC support for PCIE

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Date:	Mon, 8 Sep 2014 20:45:43 +0530
From:	Kishon Vijay Abraham I <kishon@...com>
To:	Gabriel FERNANDEZ <gabriel.fernandez@...com>,
	Rob Herring <robh+dt@...nel.org>,
	Pawel Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>,
	Srinivas Kandagatla <srinivas.kandagatla@...il.com>,
	Maxime Coquelin <maxime.coquelin@...com>,
	Patrice Chotard <patrice.chotard@...com>,
	Russell King <linux@....linux.org.uk>,
	Grant Likely <grant.likely@...aro.org>
CC:	<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
	<linux-arm-kernel@...ts.infradead.org>, <kernel@...inux.com>,
	Gabriel Fernandez <gabriel.fernandez@...aro.org>,
	Harsh Gupta <harsh.gupta@...com>,
	Gabriel Fernandez <gabriel.fernandez@...aro.orgm>
Subject: Re: [PATCH v2 7/8] phy: miphy28lp: Add SSC support for PCIE



On Wednesday 03 September 2014 09:07 PM, Gabriel FERNANDEZ wrote:
> SSC is the technique of modulating the operating frequency of a signal
> slightly to spread its radiated emissions over a range of frequencies.
> This reduction in the maximum emission for a given frequency helps meet
> radiated emission requirements.
> These settings are applicable for PCIE with Internal clock.
> 
> Signed-off-by: Harsh Gupta <harsh.gupta@...com>
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@...aro.orgm>
> ---
>  drivers/phy/phy-miphy28lp.c | 32 ++++++++++++++++++++++++++++++++
>  1 file changed, 32 insertions(+)
> 
> diff --git a/drivers/phy/phy-miphy28lp.c b/drivers/phy/phy-miphy28lp.c
> index b36e737..976fdda 100644
> --- a/drivers/phy/phy-miphy28lp.c
> +++ b/drivers/phy/phy-miphy28lp.c
> @@ -679,6 +679,36 @@ static int miphy28lp_init_sata(struct miphy28lp_phy *miphy_phy)
>  	return miphy_is_ready(miphy_phy);
>  }
>  
> +static void miphy_pcie_tune_ssc(struct miphy28lp_phy *miphy_phy)
> +{
> +	u8 val;
> +
> +	/* Compensate Tx impedance to avoid out of range values */
> +	if (miphy_phy->ssc) {
> +		/*
> +		 * Enable the SSC on PLL for all banks
> +		 * SSC Modulation @ 31 KHz and 4000 ppm modulation amp
> +		 */
> +		val = readb_relaxed(miphy_phy->base + 0x0c);
> +		val |= 0x04;
> +		writeb_relaxed(val, miphy_phy->base + 0x0c);
> +		val = readb_relaxed(miphy_phy->base + 0x0a);
> +		val |= 0x10;
> +		writeb_relaxed(val, miphy_phy->base + 0x0a);

macros for these registers and values is needed. Or else it's difficult to review.
> +
> +		for (val = 0; val < 2; val++) {
> +			writeb_relaxed(val, miphy_phy->base + 0x0f);
> +			writeb_relaxed(0x69, miphy_phy->base + 0xe5);

Do these registers have to be written for every iteration?

Thanks
Kishon
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