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Date:	Thu, 25 Sep 2014 10:16:36 -0600
From:	Bjorn Helgaas <bhelgaas@...gle.com>
To:	Arnd Bergmann <arnd@...db.de>
Cc:	Sunil Kovvuri <sunil.kovvuri@...il.com>,
	LAKML <linux-arm-kernel@...ts.infradead.org>,
	Robert Richter <rric@...nel.org>,
	Rob Herring <robh+dt@...nel.org>,
	Pawel Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>,
	Catalin Marinas <catalin.marinas@....com>,
	Will Deacon <will.deacon@....com>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	linux-pci <linux-pci@...r.kernel.org>,
	Liviu Dudau <liviu.dudau@....com>,
	LKML <linux-kernel@...r.kernel.org>,
	Robert Richter <rrichter@...ium.com>,
	Sunil Goutham <sgoutham@...ium.com>
Subject: Re: [PATCH 3/6] pci, thunder: Add PCIe host controller devicetree bindings

On Thu, Sep 25, 2014 at 1:31 AM, Arnd Bergmann <arnd@...db.de> wrote:
> On Thursday 25 September 2014 00:37:00 Sunil Kovvuri wrote:
>> On Thu, Sep 25, 2014 at 12:04 AM, Arnd Bergmann <arnd@...db.de> wrote:
>> > On Wednesday 24 September 2014 23:34:04 Sunil Kovvuri wrote:

>> >> All on-board PCI devices connected to this PCI controller have fixed resources
>> >> and doesn't have to be allocated/reassigned. Some of these devices are
>> >> SRIOV based.
>> >
>> > I think you need to mark the ones that are nonrelocatable with flag
>> > 0x80000000, otherwise the PCI core might decide to reassign them.
>>
>> Is this flag part of DT pci node properties ?
>> I am using IORESOURCE_PCI_FIXED flag. Its there in other patches of
>> the same series.
>
> Ah, right. I checked the source code again and it seems that we don't handle
> this right at the moment. I think a range that has the nonrelocatable
> flag set should be used for IORESOURCE_PCI_FIXED mappings without any
> host specific code, but that needs to be implemented in common code.

What connection do you envision between nonrelocatable ranges and
IORESOURCE_PCI_FIXED?  I don't know what a nonrelocatable range is,
but for IORESOURCE_PCI_FIXED, all I intend is that the PCI core should
not try to assign a different address, e.g., because the BAR is
read-only or because it's a legacy IDE/VGA/etc. range for which there
is no BAR at all.

Bjorn
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