linux-kernel - Re: [PATCH RESEND 08/12] mmc: sdhci-pxav3: Get optional core clock

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Date:	Tue, 28 Oct 2014 10:53:21 +0100
From:	Ulf Hansson <ulf.hansson@...aro.org>
To:	Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>
Cc:	Chris Ball <chris@...ntf.net>,
	Antoine Ténart <antoine.tenart@...e-electrons.com>,
	linux-mmc <linux-mmc@...r.kernel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH RESEND 08/12] mmc: sdhci-pxav3: Get optional core clock

On 21 October 2014 11:22, Sebastian Hesselbarth
<sebastian.hesselbarth@...il.com> wrote:
> Besides the I/O clock, some PXAv3 SDHCI IP also requires a core clock to
> be enabled. Add an optional core clock to the corresponding driver.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>

Thanks! Applied for next!

Kind regards
Uffe


> ---
> Cc: Chris Ball <chris@...ntf.net>
> Cc: Ulf Hansson <ulf.hansson@...aro.org>
> Cc: "Antoine Ténart" <antoine.tenart@...e-electrons.com>
> Cc: linux-mmc@...r.kernel.org
> Cc: devicetree@...r.kernel.org
> Cc: linux-arm-kernel@...ts.infradead.org
> Cc: linux-kernel@...r.kernel.org
> ---
>  drivers/mmc/host/sdhci-pxav3.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
> index 3dfd97977515..ad0badad0ebc 100644
> --- a/drivers/mmc/host/sdhci-pxav3.c
> +++ b/drivers/mmc/host/sdhci-pxav3.c
> @@ -59,6 +59,7 @@
>  #define SDCE_MISC_INT_EN       (1<<1)
>
>  struct sdhci_pxa {
> +       struct clk *clk_core;
>         struct clk *clk_io;
>         u8      power_mode;
>  };
> @@ -320,6 +321,10 @@ static int sdhci_pxav3_probe(struct platform_device *pdev)
>         pltfm_host->clk = pxa->clk_io;
>         clk_prepare_enable(pxa->clk_io);
>
> +       pxa->clk_core = devm_clk_get(dev, "core");
> +       if (!IS_ERR(pxa->clk_core))
> +               clk_prepare_enable(pxa->clk_core);
> +
>         /* enable 1/8V DDR capable */
>         host->mmc->caps |= MMC_CAP_1_8V_DDR;
>
> @@ -392,6 +397,8 @@ err_add_host:
>  err_of_parse:
>  err_cd_req:
>         clk_disable_unprepare(pxa->clk_io);
> +       if (!IS_ERR(pxa->clk_core))
> +               clk_disable_unprepare(pxa->clk_core);
>  err_clk_get:
>  err_mbus_win:
>         sdhci_pltfm_free(pdev);
> @@ -409,6 +416,8 @@ static int sdhci_pxav3_remove(struct platform_device *pdev)
>         pm_runtime_disable(&pdev->dev);
>
>         clk_disable_unprepare(pxa->clk_io);
> +       if (!IS_ERR(pxa->clk_core))
> +               clk_disable_unprepare(pxa->clk_core);
>
>         sdhci_pltfm_free(pdev);
>
> @@ -456,6 +465,8 @@ static int sdhci_pxav3_runtime_suspend(struct device *dev)
>         spin_unlock_irqrestore(&host->lock, flags);
>
>         clk_disable_unprepare(pxa->clk_io);
> +       if (!IS_ERR(pxa->clk_core))
> +               clk_disable_unprepare(pxa->clk_core);
>
>         return 0;
>  }
> @@ -468,6 +479,8 @@ static int sdhci_pxav3_runtime_resume(struct device *dev)
>         unsigned long flags;
>
>         clk_prepare_enable(pxa->clk_io);
> +       if (!IS_ERR(pxa->clk_core))
> +               clk_prepare_enable(pxa->clk_core);
>
>         spin_lock_irqsave(&host->lock, flags);
>         host->runtime_suspended = false;
> --
> 2.1.1
>
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