linux-kernel - Re: [PATCH] perf, amd, ibs: Update IBS MSRs and feature definitions

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:	Thu, 6 Nov 2014 10:57:40 -0600
From:	Aravind Gopalakrishnan <aravind.gopalakrishnan@....com>
To:	Borislav Petkov <bp@...e.de>
CC:	<a.p.zijlstra@...llo.nl>, <paulus@...ba.org>, <mingo@...hat.com>,
	<acme@...nel.org>, <tglx@...utronix.de>, <hpa@...or.com>,
	<x86@...nel.org>, <linux-kernel@...r.kernel.org>,
	Paolo Bonzini <pbonzini@...hat.com>,
	"Jan Kiszka" <jan.kiszka@...mens.com>,
	Len Brown <len.brown@...el.com>,
	Fenghua Yu <fenghua.yu@...el.com>
Subject: Re: [PATCH] perf, amd, ibs: Update IBS MSRs and feature definitions

On 11/6/2014 10:34 AM, Borislav Petkov wrote:
> On Thu, Nov 06, 2014 at 10:26:22AM -0600, Aravind Gopalakrishnan wrote:
>> diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h
>> index e21331c..ba7b609 100644
>> --- a/arch/x86/include/uapi/asm/msr-index.h
>> +++ b/arch/x86/include/uapi/asm/msr-index.h
>> @@ -206,6 +206,8 @@
>>   #define MSR_AMD64_IBSOP_REG_MASK	((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
>>   #define MSR_AMD64_IBSCTL		0xc001103a
>>   #define MSR_AMD64_IBSBRTARGET		0xc001103b
>> +#define MSR_AMD64_IBS_FETCH_EXTD_CTL	0xc001103c
>> +#define MSR_AMD64_IBSOPDATA4		0xc001103d
>>   #define MSR_AMD64_IBS_REG_COUNT_MAX	8 /* includes MSR_AMD64_IBSBRTARGET */
>>   
>>   /* Fam 16h MSRs */
>> diff --git a/arch/x86/kernel/cpu/perf_event_amd_ibs.c b/arch/x86/kernel/cpu/perf_event_amd_ibs.c
>> index cbb1be3e..a61f5c6 100644
>> --- a/arch/x86/kernel/cpu/perf_event_amd_ibs.c
>> +++ b/arch/x86/kernel/cpu/perf_event_amd_ibs.c
>> @@ -565,6 +565,21 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
>>   				       perf_ibs->offset_max,
>>   				       offset + 1);
>>   	} while (offset < offset_max);
>> +	if (event->attr.sample_type & PERF_SAMPLE_RAW) {
>> +		/*
>> +		 * Read IbsBrTarget and IbsOpData4 separately
>> +		 * depending on their availability.
>> +		 * Can't add to offset_max as they are staggered
>> +		 */
>> +		if (ibs_caps & IBS_CAPS_BRNTRGT) {
>> +			rdmsrl(MSR_AMD64_IBSBRTARGET, *buf++);
> Are those MSRs present on everything that supports IBS and if not, you
> probably should do rdmsr_safe() here instead and handle the error case.
> Or do something with f/m/s checking or so...

But Why?
IBS_CAPS_BRNTRGT and IBS_CAPS_OPDATA4 indicate support for the 
respective MSRs and
I am only loading the MSR contents upon checking for their availability. 
So it's not like an exception is
generated for a rdmsr command on an unimplemented/reserved MSR.

And the nice thing about the feature identifiers is that I don't have to 
do f/m/s checks right?
I mean, if some other future processor decides to implement it, then we 
don't have to revisit the code
to make a change to the f/m/s condition.
And if they don't want to use those MSRs then it's still OK as the 
feature bits are not going to be set..


Thanks,
-Aravind.

>> +			size++;
>> +		}
>> +		if (ibs_caps & IBS_CAPS_OPDATA4) {
>> +			rdmsrl(MSR_AMD64_IBSOPDATA4, *buf++);
>> +			size++;
>> +		}
>> +	}
>>   	ibs_data.size = sizeof(u64) * size;
>>   
>>   	regs = *iregs;
>> -- 
>> 1.9.1
>>

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/