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Date: Wed, 19 Nov 2014 18:04:48 +0000
From: Mark Rutland <mark.rutland@....com>
To: Yingjoe Chen <yingjoe.chen@...iatek.com>
Cc: Thomas Gleixner <tglx@...utronix.de>,
Jiang Liu <jiang.liu@...ux.intel.com>,
Marc Zyngier <Marc.Zyngier@....com>,
Boris BREZILLON <boris.brezillon@...e-electrons.com>,
Russell King <linux@....linux.org.uk>,
Jason Cooper <jason@...edaemon.net>,
Pawel Moll <Pawel.Moll@....com>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"hc.yen@...iatek.com" <hc.yen@...iatek.com>,
"srv_heupstream@...iatek.com" <srv_heupstream@...iatek.com>,
"yh.chen@...iatek.com" <yh.chen@...iatek.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"grant.likely@...aro.org" <grant.likely@...aro.org>,
Yijing Wang <wangyijing@...wei.com>,
Rob Herring <robh+dt@...nel.org>,
"nathan.chung@...iatek.com" <nathan.chung@...iatek.com>,
"yingjoe.chen@...il.com" <yingjoe.chen@...il.com>,
Matthias Brugger <matthias.bgg@...il.com>,
"eddie.huang@...iatek.com" <eddie.huang@...iatek.com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Sascha Hauer <kernel@...gutronix.de>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v7 2/4] ARM: mediatek: Add sysirq interrupt polarity
support
On Wed, Nov 19, 2014 at 02:14:09PM +0000, Yingjoe Chen wrote:
> Mediatek SoCs have interrupt polarity support in sysirq which
> allows to invert polarity for given interrupt. Add this support
> using hierarchy irq domain.
>
> Signed-off-by: Yingjoe Chen <yingjoe.chen@...iatek.com>
> ---
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-mtk-sysirq.c | 158 +++++++++++++++++++++++++++++++++++++++
> 2 files changed, 159 insertions(+)
> create mode 100644 drivers/irqchip/irq-mtk-sysirq.c
>
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index 173bb5f..4e0f254 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -38,3 +38,4 @@ obj-$(CONFIG_IRQ_CROSSBAR) += irq-crossbar.o
> obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o \
> irq-bcm7120-l2.o
> obj-$(CONFIG_KEYSTONE_IRQ) += irq-keystone.o
> +obj-$(CONFIG_ARCH_MEDIATEK) += irq-mtk-sysirq.o
> diff --git a/drivers/irqchip/irq-mtk-sysirq.c b/drivers/irqchip/irq-mtk-sysirq.c
> new file mode 100644
> index 0000000..93cb945
> --- /dev/null
> +++ b/drivers/irqchip/irq-mtk-sysirq.c
> @@ -0,0 +1,158 @@
> +/*
> + * Copyright (c) 2014 MediaTek Inc.
> + * Author: Joe.C <yingjoe.chen@...iatek.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/irq.h>
> +#include <linux/irqdomain.h>
> +#include <linux/of.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_address.h>
> +#include <linux/io.h>
> +#include <linux/slab.h>
> +#include <linux/spinlock.h>
> +
> +#include "irqchip.h"
> +
> +#define MT6577_SYS_INTPOL_NUM (224)
> +
> +struct mtk_sysirq_chip_data {
> + spinlock_t lock;
> + void __iomem *intpol_base;
> +};
> +
> +static int mtk_sysirq_set_type(struct irq_data *data, unsigned int type)
> +{
> + irq_hw_number_t hwirq = data->hwirq;
> + struct mtk_sysirq_chip_data *chip_data = data->chip_data;
> + u32 offset, reg_index, value;
> + unsigned long flags;
> + int ret;
> +
> + offset = hwirq & 0x1f;
> + reg_index = hwirq >> 5;
> +
> + spin_lock_irqsave(&chip_data->lock, flags);
> + value = readl_relaxed(chip_data->intpol_base + reg_index * 4);
> + if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_EDGE_FALLING) {
> + if (type == IRQ_TYPE_LEVEL_LOW)
> + type = IRQ_TYPE_LEVEL_HIGH;
> + else
> + type = IRQ_TYPE_EDGE_RISING;
> + value |= (1 << offset);
> + } else
> + value &= ~(1 << offset);
Nit: if one branch of an if statements is bracketed, both branches
should be. Please bracket the else case.
> + writel(value, chip_data->intpol_base + reg_index * 4);
> +
> + data = data->parent_data;
> + ret = data->chip->irq_set_type(data, type);
> + spin_unlock_irqrestore(&chip_data->lock, flags);
> + return ret;
> +}
> +
> +static struct irq_chip mtk_sysirq_chip = {
> + .name = "MT_SYSIRQ",
> + .irq_mask = irq_chip_mask_parent,
> + .irq_unmask = irq_chip_unmask_parent,
> + .irq_eoi = irq_chip_eoi_parent,
> + .irq_set_type = mtk_sysirq_set_type,
> + .irq_retrigger = irq_chip_retrigger_hierarchy,
> + .irq_set_affinity = irq_chip_set_affinity_parent,
> +};
> +
> +static int mtk_sysirq_domain_xlate(struct irq_domain *d,
> + struct device_node *controller,
> + const u32 *intspec, unsigned int intsize,
> + unsigned long *out_hwirq,
> + unsigned int *out_type)
> +{
> + if (intsize < 3)
> + return -EINVAL;
> +
> + /* sysirq doesn't support PPI */
> + if (intspec[0])
> + return -EINVAL;
> +
> + *out_hwirq = intspec[1];
> + *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
All of this is very strongly tied to the GIC, but the binding made it
sound like this was more generic (it didn't specify the number of cells
or their meaning). It doesn't look like we validate that this is
attached to a GIC.
Do we expect this to only ever be attached to a GICv2?
It would be nice to either make this generic or to describe the format
in the binding.
Also, surely you expect intsize == 3 if you expect a GICv2? Likewise in
mtk_sysirq_domain_alloc.
Thanks,
Mark.
> + return 0;
> +}
> +
> +static int mtk_sysirq_domain_alloc(struct irq_domain *domain, unsigned int virq,
> + unsigned int nr_irqs, void *arg)
> +{
> + int i;
> + irq_hw_number_t hwirq;
> + struct of_phandle_args *irq_data = arg;
> + struct of_phandle_args gic_data = *irq_data;
> +
> + if (irq_data->args_count < 3)
> + return -EINVAL;
> +
> + hwirq = irq_data->args[1];
> + for (i = 0; i < nr_irqs; i++)
> + irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
> + &mtk_sysirq_chip,
> + domain->host_data);
> +
> + gic_data.np = domain->parent->of_node;
> + return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &gic_data);
> +}
> +
> +static struct irq_domain_ops sysirq_domain_ops = {
> + .xlate = mtk_sysirq_domain_xlate,
> + .alloc = mtk_sysirq_domain_alloc,
> + .free = irq_domain_free_irqs_common,
> +};
> +
> +static int __init mtk_sysirq_of_init(struct device_node *node,
> + struct device_node *parent)
> +{
> + struct irq_domain *domain, *domain_parent;
> + struct mtk_sysirq_chip_data *chip_data;
> + int ret = 0;
> +
> + domain_parent = irq_find_host(parent);
> + if (!domain_parent) {
> + pr_err("mtk_sysirq: interrupt-parent not found\n");
> + return -EINVAL;
> + }
> +
> + chip_data = kzalloc(sizeof(*chip_data), GFP_KERNEL);
> + if (!chip_data)
> + return -ENOMEM;
> +
> + chip_data->intpol_base = of_io_request_and_map(node, 0, "intpol");
> + if (!chip_data->intpol_base) {
> + pr_err("mtk_sysirq: unable to map sysirq register\n");
> + ret = -ENOMEM;
> + goto out_free;
> + }
> +
> + domain = irq_domain_add_hierarchy(domain_parent, 0,
> + MT6577_SYS_INTPOL_NUM, node,
> + &sysirq_domain_ops, chip_data);
> + if (!domain) {
> + ret = -ENOMEM;
> + goto out_unmap;
> + }
> + spin_lock_init(&chip_data->lock);
> +
> + return 0;
> +
> +out_unmap:
> + iounmap(chip_data->intpol_base);
> +out_free:
> + kfree(chip_data);
> + return ret;
> +}
> +IRQCHIP_DECLARE(mtk_sysirq, "mediatek,mt6577-sysirq", mtk_sysirq_of_init);
> --
> 1.8.1.1.dirty
>
>
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