linux-kernel - [PATCH] ARM: dts: rockchip: set dw

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Date:	Thu,  4 Dec 2014 10:49:35 +0800
From:	Addy Ke <addy.ke@...k-chips.com>
To:	heiko@...ech.de, dianders@...omium.org, amstan@...omium.org,
	sonnyrao@...omium.org, robh+dt@...nel.org, pawel.moll@....com,
	mark.rutland@....com, ijc+devicetree@...lion.org.uk,
	galak@...eaurora.org
Cc:	linux@....linux.org.uk, devicetree@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
	linux-rockchip@...ts.infradead.org, olof@...om.net,
	hj@...k-chips.com, kever.yang@...k-chips.com, xjq@...k-chips.com,
	huangtao@...k-chips.com, zyw@...k-chips.com, yzq@...k-chips.com,
	zhenfu.fang@...k-chips.com, cf@...k-chips.com,
	zhangqing@...k-chips.com, hl@...k-chips.com,
	wei.luo@...k-chips.com, Addy Ke <addy.ke@...k-chips.com>
Subject: [PATCH] ARM: dts: rockchip: set dw_mmc max-freq 150Mhz

All of mmc controllers include SDMMC, SDIO0, SDIO1, and EMMC on RK3288
are limited to 150Mhz. It was mainly caused by two reasons:
- RK3288's IO pad(except DDR IO pad) is generic, which can only support
  the max of 150Mhz.
- Mmc controller was designed at 150Mhz, and the pressure test by IC team
  was based on this freequency point.

Signed-off-by: Addy Ke <addy.ke@...k-chips.com>
---
 arch/arm/boot/dts/rk3288.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index acb6a2f..9c35a1d 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -149,6 +149,7 @@
 
 	sdmmc: dwmmc@...c0000 {
 		compatible = "rockchip,rk3288-dw-mshc";
+		clock-freq-min-max = <400000 150000000>;
 		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 		clock-names = "biu", "ciu";
 		fifo-depth = <0x100>;
@@ -159,6 +160,7 @@
 
 	sdio0: dwmmc@...d0000 {
 		compatible = "rockchip,rk3288-dw-mshc";
+		clock-freq-min-max = <400000 150000000>;
 		clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
 		clock-names = "biu", "ciu";
 		fifo-depth = <0x100>;
@@ -169,6 +171,7 @@
 
 	sdio1: dwmmc@...e0000 {
 		compatible = "rockchip,rk3288-dw-mshc";
+		clock-freq-min-max = <400000 150000000>;
 		clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
 		clock-names = "biu", "ciu";
 		fifo-depth = <0x100>;
@@ -179,6 +182,7 @@
 
 	emmc: dwmmc@...f0000 {
 		compatible = "rockchip,rk3288-dw-mshc";
+		clock-freq-min-max = <400000 150000000>;
 		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 		clock-names = "biu", "ciu";
 		fifo-depth = <0x100>;
-- 
1.8.3.2


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