linux-kernel - Re: [PATCH 09/19] clk: samsung: exynos5433: Add clocks for CMU

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Date:	Tue, 09 Dec 2014 11:35:01 +0530
From:	Pankaj Dubey <pankaj.dubey@...sung.com>
To:	Chanwoo Choi <cw00.choi@...sung.com>,
	linux-samsung-soc@...r.kernel.org, linux-kernel@...r.kernel.org
Cc:	kgene.kim@...sung.com, mark.rutland@....com, marc.zyngier@....com,
	arnd@...db.de, olof@...om.net, catalin.marinas@....com,
	will.deacon@....com, s.nawrocki@...sung.com, tomasz.figa@...il.com,
	kyungmin.park@...sung.com, inki.dae@...sung.com,
	chanho61.park@...sung.com, geunsik.lim@...sung.com,
	sw0312.kim@...sung.com, jh80.chung@...sung.com,
	a.kesavan@...sung.com, devicetree@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 09/19] clk: samsung: exynos5433: Add clocks for
 CMU_BUS{0|1|2} domains

Hi Chanwoo,

On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote:
> This patch adds the mux/divider/gate clocks for CMU_BUS{0|1|2} domains
> which contain global data buses clocked at up the 400MHz. These blocks
> transfer data between DRAM and various sub-blocks. These clock domains
> also contain global peripheral buses clocked at 67/111/200/222/266/333/400
> MHz and used for regiser accesses.

typo: %s/regiser/register

>
> Cc: Sylwester Nawrocki <s.nawrocki@...sung.com>
> Cc: Tomasz Figa <tomasz.figa@...il.com>
> Cc: Arnd Bergmann <arnd@...db.de>
> Signed-off-by: Chanwoo Choi <cw00.choi@...sung.com>
> Acked-by: Inki Dae <inki.dae@...sung.com>
> Acked-by: Geunsik Lim <geunsik.lim@...sung.com>
> ---
>   .../devicetree/bindings/clock/exynos5433-clock.txt |  21 +++
>   drivers/clk/samsung/clk-exynos5433.c               | 185 ++++++++++++++++++++-
>   include/dt-bindings/clock/exynos5433.h             |  29 +++-
>   3 files changed, 232 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
> index 9a6ae75..03ae40a 100644
> --- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
> @@ -25,6 +25,9 @@ Required Properties:
>       which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
>     - "samsung,exynos5433-cmu-aud"   - clock controller compatible for CMU_AUD
>       which generates clocks for Cortex-A5/BUS/AUDIO clocks.
> +  - "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1"
> +    and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS
> +    which generates global data buses clock and global peripheral buses clock.
>
>   - reg: physical base address of the controller and length of memory mapped
>     region.
> @@ -94,6 +97,24 @@ Example 1: Examples of clock controller nodes are listed below.
>   		#clock-cells = <1>;
>   	};
>
> +	cmu_bus0: clock-controller@...3600000 {
> +		compatible = "samsung,exynos5433-cmu-bus0";
> +		reg = <0x13600000 0x0b04>;
> +		#clock-cells = <1>;
> +	};
> +
> +	cmu_bus1: clock-controller@...4800000 {
> +		compatible = "samsung,exynos5433-cmu-bus1";
> +		reg = <0x14800000 0x0b04>;
> +		#clock-cells = <1>;
> +	};
> +
> +	cmu_bus2: clock-controller@...3400000 {
> +		compatible = "samsung,exynos5433-cmu-bus2";
> +		reg = <0x13400000 0x0b04>;
> +		#clock-cells = <1>;
> +	};
> +
>   Example 2: UART controller node that consumes the clock generated by the clock
>   	   controller.
>
> diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
> index 99262e0..5b4ec83 100644
> --- a/drivers/clk/samsung/clk-exynos5433.c
> +++ b/drivers/clk/samsung/clk-exynos5433.c
> @@ -425,7 +425,7 @@ static struct samsung_div_clock top_div_clks[] __initdata = {
>   			DIV_TOP2, 0, 3),
>
>   	/* DIV_TOP3 */
> -	DIV(CLK_DIV_ACLK_IMEM_SSSX, "div_aclk_imem_sssx",
> +	DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266",

This change can be moved to patch 1/19 itself.

>   			"mout_bus_pll_user", DIV_TOP3, 24, 3),
>   	DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200",
>   			"mout_bus_pll_user", DIV_TOP3, 20, 3),
> @@ -440,6 +440,14 @@ static struct samsung_div_clock top_div_clks[] __initdata = {
>   	DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a",
>   			"mout_bus_pll_user", DIV_TOP3, 0, 3),
>
> +	/* DIV_TOP4 */
> +	DIV(CLK_DIV_ACLK_G3D_400, "div_aclk_g3d_400", "mout_bus_pll_user",
> +			DIV_TOP4, 8, 3),
> +	DIV(CLK_DIV_ACLK_BUS0_400, "div_aclk_bus0_400", "mout_aclk_bus0_400",
> +			DIV_TOP4, 4, 3),
> +	DIV(CLK_DIV_ACLK_BUS1_400, "div_aclk_bus1_400", "mout_bus_pll_user",
> +			DIV_TOP4, 0, 3),
> +

With these changes you can have:

Reviewed-by: Pankaj Dubey <pankaj.dubey@...sung.com>

Thanks,
Pankaj Dubey
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