linux-kernel - Re: [PATCH 2/2] misc: sram: switch to ioremap

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Date:	Wed, 17 Dec 2014 18:05:00 +0530
From:	Abhilash Kesavan <kesavan.abhilash@...il.com>
To:	Catalin Marinas <catalin.marinas@....com>
Cc:	Philipp Zabel <p.zabel@...gutronix.de>,
	Will Deacon <Will.Deacon@....com>,
	Santosh Shilimkar <santosh.shilimkar@...com>,
	Tony Lindgren <tony@...mide.com>,
	"heiko@...ech.de" <heiko@...ech.de>,
	"Li.Xiubo@...escale.com" <Li.Xiubo@...escale.com>,
	"shc_work@...l.ru" <shc_work@...l.ru>,
	"nicoleotsuka@...il.com" <nicoleotsuka@...il.com>,
	"arnd@...db.de" <arnd@...db.de>,
	"gregkh@...uxfoundation.org" <gregkh@...uxfoundation.org>,
	"robh+dt@...nel.org" <robh+dt@...nel.org>,
	"grant.likely@...aro.org" <grant.likely@...aro.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"corbet@....net" <corbet@....net>,
	"padma.v@...sung.com" <padma.v@...sung.com>,
	"alsa-devel@...a-project.org" <alsa-devel@...a-project.org>,
	"shawn.guo@...escale.com" <shawn.guo@...escale.com>,
	"bcousson@...libre.com" <bcousson@...libre.com>,
	"kernel@...gutronix.de" <kernel@...gutronix.de>,
	"kgene@...nel.org" <kgene@...nel.org>,
	Pawel Moll <Pawel.Moll@....com>
Subject: Re: [PATCH 2/2] misc: sram: switch to ioremap_wc from ioremap

Hi,

On Thu, Dec 11, 2014 at 8:28 PM, Catalin Marinas
<catalin.marinas@....com> wrote:
> On Thu, Dec 11, 2014 at 11:40:46AM +0000, Philipp Zabel wrote:
>> Hi Will,
>>
>> Am Donnerstag, den 11.12.2014, 10:39 +0000 schrieb Will Deacon:
>> > On Thu, Dec 11, 2014 at 10:08:33AM +0000, Philipp Zabel wrote:
>> > > Hi Abhilash,
>> > >
>> > > Am Donnerstag, den 11.12.2014, 08:28 +0530 schrieb Abhilash Kesavan:
>> > > > Currently, the SRAM allocator returns device memory via ioremap.
>> > > > This causes issues on ARM64 when the internal SoC SRAM allocated by
>> > > > the generic sram driver is used for audio playback. The destination
>> > > > buffer address (which is ioremapped SRAM) is not 64-bit aligned for
>> > > > certain streams (e.g. 44.1k sampling rate). In such cases we get
>> > > > unhandled alignment faults. Use ioremap_wc in place of ioremap which
>> > > > gives us normal non-cacheable memory instead of device memory.
>> > >
>> > > Could this break the omap_bus_sync() implementation in
>> > > arch/arm/mach-omap2/omap4-common.c?
>> > >
>> > >     void omap_bus_sync(void)
>> > >     {
>> > >             if (dram_sync && sram_sync) {
>> > >                     writel_relaxed(readl_relaxed(dram_sync), dram_sync);
>> > >                     writel_relaxed(readl_relaxed(sram_sync), sram_sync);
>> > >                     isb();
>> > >             }
>> > >     }
>> > >
>> > > It is used in wmb() and omap_do_wfi() to drain interconnect write
>> > > buffers on omap4/5. If sram_sync is mapped with write-combining, could
>> > > the last write to sram_sync stay stuck in the write-combining buffer
>> > > until after the function returns?
>> >
>> > I think you have that issue anyway, since you can get an early write
>> > response even if you use ioremap. Does the write to sram_sync have
>> > side-effects that we need to wait for?
>>
>> [Added Tony Lindgren and Santosh Shilimkar to Cc:]
>> I don't know.
>
> In addition to Will's question, do you care about the access size?
> ioremap() returns Device memory which is bufferable (early
> acknowledgement) but it guarantees the access size. With write
> combining, you may get a different access size than requested.

>From the existing dts files, omap, imx, rockchip and exynos seem to be
the only users of the sram allocator code. I have tested this on
Exynos5420, Exynos5800 and Exynos7; there is no change in behavior
seen on these boards. Tested-by for other SoCs would be appreciated.

Regards,
Abhilash
>
> --
> Catalin
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