linux-kernel - Re: [PATCH 07/10] MIPS: support for hybrid FPRs

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Date:	Tue, 23 Dec 2014 23:31:54 +0000
From:	James Hogan <james.hogan@...tec.com>
To:	Aaro Koskinen <aaro.koskinen@....fi>
CC:	Paul Burton <paul.burton@...tec.com>,
	Ralf Baechle <ralf@...ux-mips.org>,
	<linux-mips@...ux-mips.org>,
	Alexander Viro <viro@...iv.linux.org.uk>,
	<linux-fsdevel@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 07/10] MIPS: support for hybrid FPRs

On Wed, Dec 24, 2014 at 01:21:11AM +0200, Aaro Koskinen wrote:
> Hi,
> 
> On Thu, Sep 11, 2014 at 08:30:20AM +0100, Paul Burton wrote:
> > Hybrid FPRs is a scheme where scalar FP registers are 64b wide, but
> > accesses to odd indexed single registers use bits 63:32 of the
> > preceeding even indexed 64b register. In this mode all FP code
> > except that built for the plain FP64 ABI can execute correctly. Most
> > notably a combination of FP64A & FP32 code can execute correctly,
> > allowing for existing FP32 binaries to be linked with new FP64A binaries
> > that can make use of 64 bit FP & MSA.
> 
> This commit (4227a2d4efc9c84f35826dc4d1e6dc183f6c1c05, bisected)
> in 3.19-rc1 breaks my Loongson-2F system. I get endless amount
> of "Reserved instruction in kernel code" exceptions when booting.
> See some examples below. Nothing crashes, and there is some forward
> progress, but obviously it's completely unusable.
> 
> Any ideas?
> 
> [    2.872000] Reserved instruction in kernel code[#1]:
...
> Code: 30420001  2c420001  0040202d <40038005> 2405feff  00651824  40838005  3c032000  3c052400 

0x40038005 = mfc0 v1,$16,5 = mfc0 v1,Config5

Does this help (in linux-next)?:
http://git.linux-mips.org/cgit/ralf/upstream-sfr.git/commit/?id=5bba8dec735f18fe7a2fcd8327f28ef095337ff2

Cheers
James

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