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Date:	Mon, 12 Jan 2015 14:43:14 -0700
From:	Jason Gunthorpe <jgunthorpe@...idianresearch.com>
To:	One Thousand Gnomes <gnomes@...rguk.ukuu.org.uk>
Cc:	Pavel Machek <pavel@...x.de>, atull <atull@...nsource.altera.com>,
	gregkh@...uxfoundation.org, hpa@...or.com, monstr@...str.eu,
	michal.simek@...inx.com, rdunlap@...radead.org,
	linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
	pantelis.antoniou@...sulko.com, robh+dt@...nel.org,
	grant.likely@...aro.org, iws@...o.caltech.edu,
	linux-doc@...r.kernel.org, broonie@...nel.org, philip@...ister.org,
	rubini@...dd.com, s.trumtrar@...gutronix.de, jason@...edaemon.net,
	kyle.teske@...com, nico@...aro.org, balbi@...com,
	m.chehab@...sung.com, davidb@...eaurora.org, rob@...dley.net,
	davem@...emloft.net, cesarb@...arb.net, sameo@...ux.intel.com,
	akpm@...ux-foundation.org, linus.walleij@...aro.org,
	pawel.moll@....com, mark.rutland@....com,
	ijc+devicetree@...lion.org.uk, galak@...eaurora.org,
	devel@...verdev.osuosl.org, delicious.quinoa@...il.com,
	dinguyen@...nsource.altera.com, yvanderv@...nsource.altera.com
Subject: Re: [PATCH v8 2/4] fpga manager: add sysfs interface document

On Mon, Jan 12, 2015 at 09:01:34PM +0000, One Thousand Gnomes wrote:
> There are plenty of people today who treat the FPGA as an entirely
> dynamic resource. It's not like flashing a controller, its near
> immediate.

But this is a completely different use case. Remember, there are
*megabytes* of internal state in a FPGA, and it isn't really feasible
to dump/restore that state.

It is one thing to context switch a maths algorithm that is built to
be stateless, it is quite another to context switch between, say an
ethernet core with an operating Linux Net driver doing DMA and a maths
algorithm.

A DT overlay approach where the overlay has to be unloaded to 'free'
the FPGA makes alot of sense to me for the stateful kernel driver
environment, and open/close/etc makes alot of sense for the stateless
switchable userspace environment - other than sharing configuration
code, is there any overlap between these use cases????

> Its completely dynamic and it will get more so as we switch from the
> painful world of VHDL and friends to high level parallel aware language
> compilers for FPGAs and everyone will be knocking up quick FPGA hacks.

Only for some users. In my world FPGAs are filled with bus interface
logic, ethernet controllers, memory controllers, packet processing
engines, etc. This is all incredibly stateful - both in the FPGA
itself, and in the Linux side w/ drviers. It certainly will not ever
work in the model you are talking about.

Even if the digital state could somehow be frozen, dumped and
restored, all the FPGA external interface logic has *ANALOG* state
that cannot ever be dump/restored. It just isn't feasible for that
class of application.

Jason
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