linux-kernel - Re: [PATCH v4 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining

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Date:	Wed, 18 Feb 2015 15:01:43 +0100
From:	Maxime Ripard <maxime.ripard@...e-electrons.com>
To:	Ezequiel Garcia <ezequiel.garcia@...e-electrons.com>
Cc:	Gregory Clement <gregory.clement@...e-electrons.com>,
	Jason Cooper <jason@...edaemon.net>,
	Andrew Lunn <andrew@...n.ch>,
	Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
	Brian Norris <computersforpeace@...il.com>,
	linux-mtd@...ts.infradead.org,
	Boris Brezillon <boris@...e-electrons.com>,
	Thomas Petazzoni <thomas@...e-electrons.com>,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
	Tawfik Bayouk <tawfik@...vell.com>,
	Nadav Haklai <nadavh@...vell.com>,
	Lior Amsalem <alior@...vell.com>,
	Sudhakar Gundubogula <sudhakar@...vell.com>,
	Seif Mazareeb <seif@...vell.com>, stable@...r.kernel.org
Subject: Re: [PATCH v4 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining

On Wed, Feb 18, 2015 at 10:40:02AM -0300, Ezequiel Garcia wrote:
> On 02/18/2015 07:32 AM, Maxime Ripard wrote:
> > The NDDB register holds the data that are needed by the read and write
> > commands.
> > 
> > However, during a read PIO access, the datasheet specifies that after each 32
> > bytes read in that register, when BCH is enabled, we have to make sure that the
> > RDDREQ bit is set in the NDSR register.
> > 
> > This fixes an issue that was seen on the Armada 385, and presumably other mvebu
> > SoCs, when a read on a newly erased page would end up in the driver reporting a
> > timeout from the NAND.
> > 
> > Cc: <stable@...r.kernel.org> # v3.14
> > Signed-off-by: Maxime Ripard <maxime.ripard@...e-electrons.com>
> > ---
> >  drivers/mtd/nand/pxa3xx_nand.c | 48 ++++++++++++++++++++++++++++++++++++------
> >  1 file changed, 42 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
> > index 96b0b1d27df1..bc677362bc73 100644
> > --- a/drivers/mtd/nand/pxa3xx_nand.c
> > +++ b/drivers/mtd/nand/pxa3xx_nand.c
> > @@ -480,6 +480,42 @@ static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
> >  	nand_writel(info, NDCR, ndcr | int_mask);
> >  }
> >  
> > +static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len)
> > +{
> > +	if (info->ecc_bch) {
> > +		int timeout;
> > +
> > +		/*
> > +		 * According to the datasheet, when reading from NDDB
> > +		 * with BCH enabled, after each 32 bytes reads, we
> > +		 * have to make sure that the NDSR.RDDREQ bit is set.
> > +		 *
> > +		 * Drain the FIFO 8 32 bits reads at a time, and skip
> > +		 * the polling on the last read.
> > +		 */
> > +		while (len > 8) {
> > +			__raw_readsl(info->mmio_base + NDDB, data, 8);
> > +
> > +			for (timeout = 0;
> > +			     !(nand_readl(info, NDSR) & NDSR_RDDREQ);
> > +			     timeout++) {
> > +				if (timeout >= 5) {
> > +					dev_err(&info->pdev->dev,
> > +						"Timeout on RDDREQ while draining the FIFO\n");
> > +					return;
> > +				}
> > +
> > +				mdelay(1);
> 
> This is probably a stupid nit.. but here it goes is it any
> difference if udelay is used here?
> 
> Does this makes anything better/worse?

It doesn't make any difference. On the board I've been using, we never
hit the delay.

So I really don't care about the number of retries and the sleep
behind them. I made these numbers up, feel free to come up with others
if it makes you more comfortable, but could we settle this?

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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