linux-kernel - [PATCH 1/1] X86: hyperv: Enable MSR based APIC access

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Date:	Sun, 15 Mar 2015 23:12:07 -0700
From:	"K. Y. Srinivasan" <kys@...rosoft.com>
To:	x86@...nel.org, gregkh@...uxfoundation.org,
	linux-kernel@...r.kernel.org, devel@...uxdriverproject.org,
	olaf@...fle.de, apw@...onical.com, jasowang@...hat.com,
	tglx@...utronix.de, hpa@...or.com
Cc:	"K. Y. Srinivasan" <kys@...rosoft.com>
Subject: [PATCH 1/1] X86: hyperv: Enable MSR based APIC access

If the hypervisor supports MSR based access to the APIC registers
(EOI, TPR and ICR), implement the MSR based access.

Signed-off-by: K. Y. Srinivasan <kys@...rosoft.com>
---
 arch/x86/include/uapi/asm/hyperv.h |    5 +++
 arch/x86/kernel/cpu/mshyperv.c     |   69 ++++++++++++++++++++++++++++++++++++
 2 files changed, 74 insertions(+), 0 deletions(-)

diff --git a/arch/x86/include/uapi/asm/hyperv.h b/arch/x86/include/uapi/asm/hyperv.h
index 90c458e..6ce69e0 100644
--- a/arch/x86/include/uapi/asm/hyperv.h
+++ b/arch/x86/include/uapi/asm/hyperv.h
@@ -140,6 +140,11 @@
  */
 #define HV_X64_RELAXED_TIMING_RECOMMENDED	(1 << 5)
 
+/*
+ * Recommend using x2APIC MSRs.
+ */
+#define HV_X64_X2APIC_MSRS_RECOMMENDED       (1 << 8)
+
 /* MSR used to identify the guest OS. */
 #define HV_X64_MSR_GUEST_OS_ID			0x40000000
 
diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c
index 939155f..dd2eb49 100644
--- a/arch/x86/kernel/cpu/mshyperv.c
+++ b/arch/x86/kernel/cpu/mshyperv.c
@@ -110,6 +110,55 @@ static struct clocksource hyperv_cs = {
 	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
+static u64 ms_hv_apic_icr_read(void)
+{
+	u64 reg_val;
+
+	rdmsrl(HV_X64_MSR_ICR, reg_val);
+	return reg_val;
+}
+
+static void ms_hv_apic_icr_write(u32 low, u32 id)
+{
+	u64 reg_val;
+
+	reg_val = SET_APIC_DEST_FIELD(id);
+	reg_val = (reg_val << 32);
+	reg_val |= low;
+
+	wrmsrl(HV_X64_MSR_EOI, reg_val);
+}
+
+static u32 ms_hv_apic_read(u32 reg)
+{
+	u64 reg_val;
+
+	switch (reg) {
+	case APIC_EOI:
+	case APIC_TASKPRI:
+		rdmsrl(HV_X64_MSR_EOI, reg_val);
+		return reg_val;
+
+	default:
+		return native_apic_mem_read(reg);
+	}
+}
+
+static void ms_hv_apic_write(u32 reg, u32 val)
+{
+	u64 reg_val;
+
+	reg_val =  val;
+	switch (reg) {
+	case APIC_EOI:
+	case APIC_TASKPRI:
+		wrmsrl(HV_X64_MSR_EOI, reg_val);
+	default:
+		native_apic_mem_write(reg, val);
+	}
+}
+
+
 static void __init ms_hyperv_init_platform(void)
 {
 	/*
@@ -143,11 +192,31 @@ static void __init ms_hyperv_init_platform(void)
 	no_timer_check = 1;
 #endif
 
+	if (ms_hyperv.features & HV_X64_MSR_APIC_ACCESS_AVAILABLE) {
+		/*
+		 * Setup the hooks for optimized APIC read/write.
+		 */
+		apic->read = ms_hv_apic_read;
+		apic->write = ms_hv_apic_write;
+		apic->icr_write = ms_hv_apic_icr_write;
+		apic->icr_read = ms_hv_apic_icr_read;
+		apic->eoi_write = ms_hv_apic_write;
+	}
+
+}
+
+static bool ms_hyperv_x2apic(void)
+{
+	if (ms_hyperv.hints & HV_X64_X2APIC_MSRS_RECOMMENDED)
+		return true;
+	else
+		return false;
 }
 
 const __refconst struct hypervisor_x86 x86_hyper_ms_hyperv = {
 	.name			= "Microsoft HyperV",
 	.detect			= ms_hyperv_platform,
 	.init_platform		= ms_hyperv_init_platform,
+	.x2apic_available	= ms_hyperv_x2apic
 };
 EXPORT_SYMBOL(x86_hyper_ms_hyperv);
-- 
1.7.4.1

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