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Date:	Mon, 30 Mar 2015 20:31:38 +0200
From:	Sascha Hauer <s.hauer@...gutronix.de>
To:	Joe Perches <joe@...ches.com>
Cc:	Mike Turquette <mturquette@...aro.org>,
	Stephen Boyd <sboyd@...eaurora.org>,
	YH Chen <yh.chen@...iatek.com>, linux-kernel@...r.kernel.org,
	Henry Chen <henryc.chen@...iatek.com>,
	linux-mediatek@...ts.infradead.org, kernel@...gutronix.de,
	Matthias Brugger <matthias.bgg@...il.com>,
	Yingjoe Chen <Yingjoe.Chen@...iatek.com>,
	Eddie Huang <eddie.huang@...iatek.com>,
	linux-arm-kernel@...ts.infradead.org,
	James Liao <jamesjj.liao@...iatek.com>
Subject: Re: [PATCH 2/6] clk: mediatek: Add initial common clock support for
 Mediatek SoCs.

On Mon, Mar 30, 2015 at 10:55:46AM -0700, Joe Perches wrote:
> On Mon, 2015-03-30 at 19:40 +0200, Sascha Hauer wrote:
> > This patch adds common clock support for Mediatek SoCs, including plls,
> > muxes and clock gates.
> 
> trivia:
> 
> > diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
> 
> > +static int mtk_cg_bit_is_cleared(struct clk_hw *hw)
> > +{
> []
> > +	return val == 0;
> > +}
> > +
> > +static int mtk_cg_bit_is_set(struct clk_hw *hw)
> > +{
> []
> > +	return val != 0;
> > +}
> 
> These functions may be better returning a bool

The return type of these functions is forced by function prototype in
struct clk_ops.

Sascha

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