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Date: Sat, 18 Apr 2015 03:14:28 -0700 From: tip-bot for Kan Liang <tipbot@...or.com> To: linux-tip-commits@...r.kernel.org Cc: hpa@...or.com, mingo@...nel.org, tglx@...utronix.de, kan.liang@...el.com, peterz@...radead.org, linux-kernel@...r.kernel.org, ak@...ux.intel.com Subject: [tip:perf/urgent] perf/x86/intel: Add Broadwell support for the LBR callstack Commit-ID: 78d504bcd769cc496f63b626f507039eab2316b7 Gitweb: http://git.kernel.org/tip/78d504bcd769cc496f63b626f507039eab2316b7 Author: Kan Liang <kan.liang@...el.com> AuthorDate: Thu, 2 Apr 2015 04:12:57 -0400 Committer: Ingo Molnar <mingo@...nel.org> CommitDate: Fri, 17 Apr 2015 09:59:07 +0200 perf/x86/intel: Add Broadwell support for the LBR callstack Same as Haswell, Broadwell also support the LBR callstack. Signed-off-by: Kan Liang <kan.liang@...el.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org> Acked-by: Andi Kleen <ak@...ux.intel.com> Link: http://lkml.kernel.org/r/1427962377-40955-1-git-send-email-kan.liang@intel.com Signed-off-by: Ingo Molnar <mingo@...nel.org> --- arch/x86/kernel/cpu/perf_event_intel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index 9da2400..219d3fb 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -3275,7 +3275,7 @@ __init int intel_pmu_init(void) hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; - intel_pmu_lbr_init_snb(); + intel_pmu_lbr_init_hsw(); x86_pmu.event_constraints = intel_bdw_event_constraints; x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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