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Date:	Thu, 23 Apr 2015 14:50:43 -0500
From:	Josh Cartwright <joshc@...com>
To:	Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri@...inx.com>
Cc:	robh+dt@...nel.org, pawel.moll@....com, mark.rutland@....com,
	ijc+devicetree@...lion.org.uk, galak@...eaurora.org,
	rob@...dley.net, michal.simek@...inx.com, grant.likely@...aro.org,
	gregkh@...uxfoundation.org, jason@...edaemon.net,
	ezequiel.garcia@...e-electrons.com, arnd@...db.de,
	dwmw2@...radead.org, computersforpeace@...il.com,
	artem.bityutskiy@...ux.intel.com, jussi.kivilinna@....fi,
	acourbot@...dia.com, ivan.khoronzhuk@...com, joern@...fs.org,
	devicetree@...r.kernel.org, linux-doc@...r.kernel.org,
	linux-kernel@...r.kernel.org, linux-mtd@...ts.infradead.org,
	kpc528@...il.com, kalluripunnaiahchoudary@...il.com,
	Punnaiah Choudary Kalluri <punnaia@...inx.com>
Subject: Re: [PATCH v6 1/2] Devicetree: Add pl353 smc controller devicetree
 binding information

Hey Punnaiah-

A few nitpicks here, in case you'll be spinning up a new version of your
patchset.

On Mon, Apr 13, 2015 at 09:41:51PM +0530, Punnaiah Choudary Kalluri wrote:
> Add pl353 static memory controller devicetree binding information.
>
> Signed-off-by: Punnaiah Choudary Kalluri <punnaia@...inx.com>
[..]
> @@ -0,0 +1,37 @@
> +Device tree bindings for ARM PL353 static memory controller
> +
> +PL353 static memory controller supports two kinds of memory
> +interfaces. i.e NAND and SRAM/NOR interfaces.
> +The actual devices are instantiated from the child nodes of pl353 smc node.
> +
> +Required properties:
> +- compatible		: Should be "arm,pl353-smc-r2p1"
> +- reg			: Controller registers map and length.
> +- clock-names		: List of input clock names - "memclk", "aclk"
> +			  (See clock bindings for details).
> +- clocks		: Clock phandles (see clock bindings for details).

Technically not clock phandles, but clock specifiers.

> +- address-cells	: Address cells, must be 1.
> +- size-cells		: Size cells. Must be 1.

These should have the leading '#' as in '#address-cells' and
'#size-cells'.

  Josh

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