linux-kernel - Re: [PATCH 0/4] Enable deferred error interrupts

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Date:	Fri, 1 May 2015 09:50:44 -0500
From:	Aravind Gopalakrishnan <aravind.gopalakrishnan@....com>
To:	Ingo Molnar <mingo@...nel.org>
CC:	<tglx@...utronix.de>, <mingo@...hat.com>, <hpa@...or.com>,
	<tony.luck@...el.com>, <bp@...en8.de>, <jiang.liu@...ux.intel.com>,
	<yinghai@...nel.org>, <x86@...nel.org>, <dvlasenk@...hat.com>,
	<JBeulich@...e.com>, <slaoub@...il.com>, <luto@...capital.net>,
	<dave.hansen@...ux.intel.com>, <oleg@...hat.com>,
	<rostedt@...dmis.org>, <rusty@...tcorp.com.au>,
	<prarit@...hat.com>, <linux@...musvillemoes.dk>, <jroedel@...e.de>,
	<andriy.shevchenko@...ux.intel.com>, <macro@...ux-mips.org>,
	<wangnan0@...wei.com>, <linux-kernel@...r.kernel.org>,
	<linux-edac@...r.kernel.org>
Subject: Re: [PATCH 0/4] Enable deferred error interrupts

On 5/1/2015 2:18 AM, Ingo Molnar wrote:
> * Aravind Gopalakrishnan <Aravind.Gopalakrishnan@....com> wrote:
>
>> Newer AMD processors can generate deferred errors and can be configured
>> to generate APIC interrupts on such events.
> What's the wider context of this? What is it good for?
>
> I suspect it's MCE related, but only from the diffstat:

Deferred errors indicate error conditions that were not corrected, but 
require no action from S/W (or action is optional).
These errors provide info about a latent UC MCE that can occur when a 
poisoned data is consumed by the processor.

HTH,

I shall include the short description in the cover letter of V2.

Thanks,
-Aravind.


>>   arch/x86/kernel/cpu/mcheck/mce.c         |   1 +
>>   arch/x86/kernel/cpu/mcheck/mce_amd.c     | 105 ++++++++++++++++++++++++++++++-
> Please provide proper high level description for the changes.
>
>


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