lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:	Tue, 05 May 2015 09:16:02 +0530
From:	Preeti U Murthy <preeti@...ux.vnet.ibm.com>
To:	Shilpasri G Bhat <shilpa.bhat@...ux.vnet.ibm.com>,
	linuxppc-dev@...abs.org, linux-kernel@...r.kernel.org
CC:	viresh.kumar@...aro.org, rjw@...ysocki.net,
	linux-pm@...r.kernel.org
Subject: Re: [PATCH v3 5/6] cpufreq: powernv: Report Psafe only if PMSR.psafe_mode_active
 bit is set

On 05/04/2015 02:24 PM, Shilpasri G Bhat wrote:
> On a reset cycle of OCC, although the system retires from safe
> frequency state the local pstate is not restored to Pmin or last
> requested pstate. Now if the cpufreq governor initiates a pstate
> change, the local pstate will be in Psafe and we will be reporting a
> false positive when we are not throttled.
> 
> So in powernv_cpufreq_throttle_check() remove the condition which
> checks if local pstate is less than Pmin while checking for Psafe
> frequency. If the cpus are forced to Psafe then PMSR.psafe_mode_active
> bit will be set. So, when OCCs become active this bit will be cleared.
> Let us just rely on this bit for reporting throttling.
> 
> Signed-off-by: Shilpasri G Bhat <shilpa.bhat@...ux.vnet.ibm.com>
> ---
>  drivers/cpufreq/powernv-cpufreq.c | 12 +++---------
>  1 file changed, 3 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/cpufreq/powernv-cpufreq.c b/drivers/cpufreq/powernv-cpufreq.c
> index 9618813..0a59d5b 100644
> --- a/drivers/cpufreq/powernv-cpufreq.c
> +++ b/drivers/cpufreq/powernv-cpufreq.c
> @@ -39,7 +39,6 @@
>  #define PMSR_PSAFE_ENABLE	(1UL << 30)
>  #define PMSR_SPR_EM_DISABLE	(1UL << 31)
>  #define PMSR_MAX(x)		((x >> 32) & 0xFF)
> -#define PMSR_LP(x)		((x >> 48) & 0xFF)
>  #define OCC_RESET		0
>  #define OCC_LOAD		1
>  #define OCC_THROTTLE		2
> @@ -316,7 +315,7 @@ static void powernv_cpufreq_throttle_check(void *data)
>  {
>  	unsigned int cpu = smp_processor_id();
>  	unsigned long pmsr;
> -	int pmsr_pmax, pmsr_lp, i;
> +	int pmsr_pmax, i;
>  
>  	pmsr = get_pmspr(SPRN_PMSR);
>  
> @@ -338,14 +337,9 @@ static void powernv_cpufreq_throttle_check(void *data)
>  			chips[i].id, pmsr_pmax);
>  	}
>  
> -	/*
> -	 * Check for Psafe by reading LocalPstate
> -	 * or check if Psafe_mode_active is set in PMSR.
> -	 */
> +	/* Check if Psafe_mode_active is set in PMSR. */
>  next:
> -	pmsr_lp = (s8)PMSR_LP(pmsr);
> -	if ((pmsr_lp < powernv_pstate_info.min) ||
> -				(pmsr & PMSR_PSAFE_ENABLE)) {
> +	if (pmsr & PMSR_PSAFE_ENABLE) {
>  		throttled = true;
>  		pr_info("Pstate set to safe frequency\n");
>  	}
> 

Reviewed-by: Preeti U Murthy <preeti@...ux.vnet.ibm.com>

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ