linux-kernel - RE: [RFC PATCH 1/2] devicetree: Add devicetree bindings documentation for ZynqMP GQSPI

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:	Thu, 21 May 2015 12:42:23 +0000
From:	Ranjit Abhimanyu Waghmode <ranjit.waghmode@...inx.com>
To:	Soren Brinkmann <sorenb@...inx.com>
CC:	"robh+dt@...nel.org" <robh+dt@...nel.org>,
	"pawel.moll@....com" <pawel.moll@....com>,
	"mark.rutland@....com" <mark.rutland@....com>,
	"ijc+devicetree@...lion.org.uk" <ijc+devicetree@...lion.org.uk>,
	"galak@...eaurora.org" <galak@...eaurora.org>,
	Michal Simek <michals@...inx.com>,
	"broonie@...nel.org" <broonie@...nel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-spi@...r.kernel.org" <linux-spi@...r.kernel.org>,
	Harini Katakam <harinik@...inx.com>,
	"Punnaiah Choudary Kalluri" <punnaia@...inx.com>,
	"ran27jit@...il.com" <ran27jit@...il.com>
Subject: RE: [RFC PATCH 1/2] devicetree: Add devicetree bindings
 documentation for ZynqMP GQSPI

Hi Soren,

On Wed, 2015-05-20 at 12:57PM +0530, Ranjit Waghmode wrote:
> Add bindings documentation for GQSPI controller driver used by Zynq 
> Ultrascale+ MPSoC
> 
> Signed-off-by: Ranjit Waghmode <ranjit.waghmode@...inx.com>
> ---
>  .../devicetree/bindings/spi/spi-zynqmp-qspi.txt    | 26 ++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt
> 
> diff --git a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt 
> b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt
> new file mode 100644
> index 0000000..cec6330
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt
> @@ -0,0 +1,26 @@
> +Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings
> +-------------------------------------------------------------------
> +
> +Required properties:
> +- compatible		: Should be "xlnx,zynqmp-qspi-1.0".
> +- reg			: Physical base address and size of GQSPI registers map.
> +- interrupts		: Property with a value describing the interrupt
> +			  number.
> +- interrupt-parent	: Must be core interrupt controller.
> +- clock-names		: List of input clock names - "ref_clk", "pclk"
> +			  (See clock bindings for details).
> +- clocks		: Clock phandles (see clock bindings for details).
> +
> +Optional properties:
> +- num-cs		: Number of chip selects used.
> +
> +Example:
> +	qspi: spi@...f0000 {
> +		compatible = "xlnx,zynqmp-qspi-1.0";
> +		clock-names = "ref_clk", "pclk";
> +		clocks = <&misc_clk &misc_clk>;
> +		interrupts = <0 15 4>;
> +		interrupt-parent = <&gic>;
> +		num-cs = <1>;
> +		reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>;

I find things a lot easier to read when there is something separating the groups. Could this become:
	reg = <0x0 0xff0f0000 0x1000>, <0x0 0xc0000000 0x8000000>; ?

[Ranjit]: I will try your suggestion and send you in the next version.

Regards,
Ranjit