linux-kernel - [tip:perf/core] perf/x86/intel/cqm: Avoid pointless MSR write

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Date:	Wed, 27 May 2015 03:03:49 -0700
From:	tip-bot for Thomas Gleixner <tipbot@...or.com>
To:	linux-tip-commits@...r.kernel.org
Cc:	peterz@...radead.org, hpa@...or.com, torvalds@...ux-foundation.org,
	linux-kernel@...r.kernel.org, matt.fleming@...el.com,
	will.auld@...el.com, vikas.shivappa@...ux.intel.com,
	tglx@...utronix.de, mingo@...nel.org, kanaka.d.juvva@...el.com
Subject: [tip:perf/core] perf/x86/intel/cqm: Avoid pointless MSR write

Commit-ID:  0bac237845e203dd1439cfc571b1baf1b2274b3b
Gitweb:     http://git.kernel.org/tip/0bac237845e203dd1439cfc571b1baf1b2274b3b
Author:     Thomas Gleixner <tglx@...utronix.de>
AuthorDate: Tue, 19 May 2015 00:00:55 +0000
Committer:  Ingo Molnar <mingo@...nel.org>
CommitDate: Wed, 27 May 2015 09:17:40 +0200

perf/x86/intel/cqm: Avoid pointless MSR write

If the usage counter is non-zero there is no point to update the rmid
in the PQR MSR.

Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
Acked-by: Matt Fleming <matt.fleming@...el.com>
Cc: Kanaka Juvva <kanaka.d.juvva@...el.com>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Vikas Shivappa <vikas.shivappa@...ux.intel.com>
Cc: Will Auld <will.auld@...el.com>
Link: http://lkml.kernel.org/r/20150518235150.080844281@linutronix.de
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
 arch/x86/kernel/cpu/perf_event_intel_cqm.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel_cqm.c b/arch/x86/kernel/cpu/perf_event_intel_cqm.c
index 63391f8..2ce69c0 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_cqm.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_cqm.c
@@ -974,10 +974,12 @@ static void intel_cqm_event_start(struct perf_event *event, int mode)
 
 	event->hw.cqm_state &= ~PERF_HES_STOPPED;
 
-	if (state->cnt++)
-		WARN_ON_ONCE(state->rmid != rmid);
-	else
+	if (state->cnt++) {
+		if (!WARN_ON_ONCE(state->rmid != rmid))
+			return;
+	} else {
 		WARN_ON_ONCE(state->rmid);
+	}
 
 	state->rmid = rmid;
 	/*
--
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