linux-kernel - Re: [PATCH 0/2] Add MT8173 MMPLL change rate support

Open Source and information security mailing list archives

Date:	Wed, 8 Jul 2015 16:49:54 +0800
From:	James Liao <jamesjj.liao@...iatek.com>
To:	Matthias Brugger <matthias.bgg@...il.com>,
	Heiko Stubner <heiko@...ech.de>,
	Stephen Boyd <sboyd@...eaurora.org>,
	Mike Turquette <mturquette@...libre.com>,
	Sascha Hauer <kernel@...gutronix.de>
CC:	<devicetree@...r.kernel.org>, <srv_heupstream@...iatek.com>,
	<linux-kernel@...r.kernel.org>, Ricky Liang <jcliang@...omium.org>,
	"Rob Herring" <robh+dt@...nel.org>,
	<linux-mediatek@...ts.infradead.org>,
	<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH 0/2] Add MT8173 MMPLL change rate support

Hi all,

The cover letter's title should be "[PATCH v2 0/2] ..."

changes since v1:
- Add a separated patch for mtk_pll_set_rate_regs().
- Use a structure array to describe a div_table.
- Limit max frequency to div_table[0].
- Minor changes such as static and comments.

Best regards,

James

On Wed, 2015-07-08 at 16:37 +0800, James Liao wrote:
> MT8173 MMPLL frequency settings are different from common PLLs.
> It needs different post divider settings for some ranges of frequency.
> This patch add support for MT8173 MMPLL frequency setting, includes:
> 
> 1. Add div-rate table for PLLs.
> 2. Increase the max ost divider setting from 3 (/8) to 4 (/16).
> 3. Write postdiv and pcw settings at the same time.
> 
> James Liao (2):
>   clk: mediatek: Fix PLL registers setting flow
>   clk: mediatek: Add MT8173 MMPLL change rate support
> 
>  drivers/clk/mediatek/clk-mt8173.c | 24 +++++++++++++++++++++---
>  drivers/clk/mediatek/clk-mtk.h    |  6 ++++++
>  drivers/clk/mediatek/clk-pll.c    | 39 +++++++++++++++++++++++++++------------
>  3 files changed, 54 insertions(+), 15 deletions(-)
> 
> --
> 1.8.1.1.dirty
> 
> 
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@...ts.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

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