linux-kernel - [PATCH 25/26] drm/msm/dsi: Convert to clk

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Date:	Fri, 31 Jul 2015 10:04:05 -0700
From:	Stephen Boyd <sboyd@...eaurora.org>
To:	Mike Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...eaurora.org>
Cc:	linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org,
	Wentao Xu <wentaox@...eaurora.org>,
	Rob Clark <robdclark@...il.com>
Subject: [PATCH 25/26] drm/msm/dsi: Convert to clk_hw based provider APIs

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.

Cc: Wentao Xu <wentaox@...eaurora.org>
Cc: Rob Clark <robdclark@...il.com>
Signed-off-by: Stephen Boyd <sboyd@...eaurora.org>
---
 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
index eb8ac3097ff5..18b7727bdc57 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
@@ -455,7 +455,7 @@ static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll)
 	cached_state->postdiv1 =
 			pll_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG);
 	cached_state->byte_mux = pll_read(base + REG_DSI_28nm_PHY_PLL_VREG_CFG);
-	cached_state->vco_rate = __clk_get_rate(pll->clk_hw.clk);
+	cached_state->vco_rate = clk_hw_get_rate(&pll->clk_hw);
 }
 
 static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll)
@@ -466,7 +466,7 @@ static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll)
 	int ret;
 
 	if ((cached_state->vco_rate != 0) &&
-		(cached_state->vco_rate == __clk_get_rate(pll->clk_hw.clk))) {
+		(cached_state->vco_rate == clk_hw_get_rate(&pll->clk_hw))) {
 		ret = dsi_pll_28nm_clk_set_rate(&pll->clk_hw,
 						cached_state->vco_rate, 0);
 		if (ret) {
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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