linux-kernel - [PATCH v10 7/8] staging: simple-fpga-bus: add TODO document

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Date:	Thu, 13 Aug 2015 12:37:31 -0500
From:	<atull@...nsource.altera.com>
To:	<gregkh@...uxfoundation.org>, <jgunthorpe@...idianresearch.com>,
	<hpa@...or.com>, <monstr@...str.eu>, <michal.simek@...inx.com>,
	<rdunlap@...radead.org>
CC:	Moritz Fischer <moritz.fischer@...us.com>,
	<linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
	<pantelis.antoniou@...sulko.com>, <robh+dt@...nel.org>,
	<grant.likely@...aro.org>, <iws@...o.caltech.edu>,
	<linux-doc@...r.kernel.org>, <pavel@...x.de>, <broonie@...nel.org>,
	<philip@...ister.org>, <rubini@...dd.com>,
	<s.trumtrar@...gutronix.de>, <jason@...edaemon.net>,
	<kyle.teske@...com>, <nico@...aro.org>, <balbi@...com>,
	<m.chehab@...sung.com>, <davidb@...eaurora.org>, <rob@...dley.net>,
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	<sameo@...ux.intel.com>, <akpm@...ux-foundation.org>,
	<linus.walleij@...aro.org>, <pawel.moll@....com>,
	<mark.rutland@....com>, <ijc+devicetree@...lion.org.uk>,
	<galak@...eaurora.org>, <devel@...verdev.osuosl.org>,
	Petr Cvek <petr.cvek@....cz>, <delicious.quinoa@...il.com>,
	<dinguyen@...nsource.altera.com>,
	Alan Tull <atull@...nsource.altera.com>
Subject: [PATCH v10 7/8] staging: simple-fpga-bus: add TODO document

From: Alan Tull <atull@...nsource.altera.com>

Add a TODO document for the simple fpga bus.

Signed-off-by: Alan Tull <atull@...nsource.altera.com>
---
v10: This patch added in v10 of the patch set
---
 drivers/staging/simple-fpga-bus/TODO |   13 +++++++++++++
 1 file changed, 13 insertions(+)
 create mode 100644 drivers/staging/simple-fpga-bus/TODO

diff --git a/drivers/staging/simple-fpga-bus/TODO b/drivers/staging/simple-fpga-bus/TODO
new file mode 100644
index 0000000..c218a57
--- /dev/null
+++ b/drivers/staging/simple-fpga-bus/TODO
@@ -0,0 +1,13 @@
+TODO:
+
+This simple-fpga-bus design avoids adding a new FPGA bridge framework as
+another dependency.  FPGA bridges are seen as phandles to resets.  I'd like
+to see if this will work for people.
+
+	- Waiting on configfs interface for DT Overlays
+	- Are the simple-fpga-bus bindings acceptable?
+	- Children don't get populated if FPGA manager is a module. Not a
+	  problem if FPGA manager is built in.
+
+Patches to:
+	Alan Tull <atull@...nsource.altera.com>
-- 
1.7.9.5

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