linux-kernel - [tip:x86/cpufeature] x86/cpufeatures: Enable cpuid for Intel SHA extensions

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Date:	Sat, 22 Aug 2015 02:21:34 -0700
From:	tip-bot for Tim Chen <tipbot@...or.com>
To:	linux-tip-commits@...r.kernel.org
Cc:	herbert@...dor.apana.org.au, bp@...e.de, dave.hansen@...el.com,
	mingo@...nel.org, tglx@...utronix.de, mouli_7982@...oo.com,
	tim.c.chen@...ux.intel.com, linux-kernel@...r.kernel.org,
	hpa@...or.com
Subject: [tip:x86/cpufeature] x86/cpufeatures:
  Enable cpuid for Intel SHA extensions

Commit-ID:  488ca7d72d974e3c00ae73ed9f947590680bdf00
Gitweb:     http://git.kernel.org/tip/488ca7d72d974e3c00ae73ed9f947590680bdf00
Author:     Tim Chen <tim.c.chen@...ux.intel.com>
AuthorDate: Fri, 21 Aug 2015 14:56:46 -0700
Committer:  Thomas Gleixner <tglx@...utronix.de>
CommitDate: Sat, 22 Aug 2015 11:17:31 +0200

x86/cpufeatures: Enable cpuid for Intel SHA extensions

Add Intel CPUID for Intel Secure Hash Algorithm Extensions. This feature
provides new instructions for accelerated computation of SHA-1 and SHA-256.
This allows the feature to be shown in the /proc/cpuinfo for cpus that
support it.

Refer to SHA extension programming guide in chapter 8.2 of the Intel
Architecture Instruction Set Extensions Programming reference
for definition of this feature's cpuid: CPUID.(EAX=07H, ECX=0):EBX.SHA [bit 29] = 1
https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf

Originally-by: Chandramouli Narayanan <mouli_7982@...oo.com>
Signed-off-by: Tim Chen <tim.c.chen@...ux.intel.com>
Cc: Borislav Petkov <bp@...e.de>
Cc: Dave Hansen <dave.hansen@...el.com>
Cc: Herbert Xu <herbert@...dor.apana.org.au>
Link: http://lkml.kernel.org/r/1440194206.3940.6.camel@schen9-mobl2
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
---
 arch/x86/include/asm/cpufeature.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 3d6606f..a94f83d 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -239,6 +239,7 @@
 #define X86_FEATURE_AVX512PF	( 9*32+26) /* AVX-512 Prefetch */
 #define X86_FEATURE_AVX512ER	( 9*32+27) /* AVX-512 Exponential and Reciprocal */
 #define X86_FEATURE_AVX512CD	( 9*32+28) /* AVX-512 Conflict Detection */
+#define X86_FEATURE_SHA_NI	( 9*32+29) /* SHA1/SHA256 Instruction Extensions */
 
 /* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */
 #define X86_FEATURE_XSAVEOPT	(10*32+ 0) /* XSAVEOPT */
--
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