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Date: Sat, 19 Sep 2015 23:45:42 +0530
From: Poonam Aggrwal <poonam.aggrwal@...escale.com>
To: <linuxppc-dev@...ts.ozlabs.org>, <linux-kernel@...r.kernel.org>,
<devicetree-discuss@...ts.ozlabs.org>
CC: <scottwood@...escale.com>,
Poonam Aggrwal <poonam.aggrwal@...escale.com>,
Shaveta Leekha <shaveta@...escale.com>
Subject: [PATCH 1/4]fsl/powerpc/b4860: Renamed the L2 caches
To make provision for more than one L2 caches in the system, change the name
from L2 to L2_1; same as in T4 platforms.
* Also remove the L2 entry from common file
"arch/powerpc/boot/dts/fsl/b4si-post.dtsi"
Keep them only in separate files for b4860 and b4420.
Signed-off-by: Shaveta Leekha <shaveta@...escale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@...escale.com>
---
- based of: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
branch master
arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 4 +++-
arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi | 4 ++--
arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 4 +++-
arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi | 8 ++++----
arch/powerpc/boot/dts/fsl/b4si-post.dtsi | 6 ------
5 files changed, 12 insertions(+), 14 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
index 1ea8602..f996cce 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
@@ -89,7 +89,9 @@
compatible = "fsl,b4420-rcpm", "fsl,qoriq-rcpm-2.0";
};
- L2: l2-cache-controller@...000 {
+ L2_1: l2-cache-controller@...000 {
compatible = "fsl,b4420-l2-cache-controller";
+ reg = <0xc20000 0x40000>;
+ next-level-cache = <&cpc>;
};
};
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
index 338af7e..4257a77 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
@@ -65,14 +65,14 @@
device_type = "cpu";
reg = <0 1>;
clocks = <&mux0>;
- next-level-cache = <&L2>;
+ next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
cpu1: PowerPC,e6500@2 {
device_type = "cpu";
reg = <2 3>;
clocks = <&mux0>;
- next-level-cache = <&L2>;
+ next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
};
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
index d1e26a7..be91803 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -258,7 +258,9 @@
compatible = "fsl,b4860-rcpm", "fsl,qoriq-rcpm-2.0";
};
- L2: l2-cache-controller@...000 {
+ L2_1: l2-cache-controller@...000 {
compatible = "fsl,b4860-l2-cache-controller";
+ reg = <0xc20000 0x40000>;
+ next-level-cache = <&cpc>;
};
};
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
index 1948f73..6823caa 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
@@ -65,28 +65,28 @@
device_type = "cpu";
reg = <0 1>;
clocks = <&mux0>;
- next-level-cache = <&L2>;
+ next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
cpu1: PowerPC,e6500@2 {
device_type = "cpu";
reg = <2 3>;
clocks = <&mux0>;
- next-level-cache = <&L2>;
+ next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
cpu2: PowerPC,e6500@4 {
device_type = "cpu";
reg = <4 5>;
clocks = <&mux0>;
- next-level-cache = <&L2>;
+ next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
cpu3: PowerPC,e6500@6 {
device_type = "cpu";
reg = <6 7>;
clocks = <&mux0>;
- next-level-cache = <&L2>;
+ next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
};
diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
index 603910a..d45ff04 100644
--- a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
@@ -465,10 +465,4 @@
bman: bman@...000 {
interrupts = <16 2 1 29>;
};
-
- L2: l2-cache-controller@...000 {
- compatible = "fsl,b4-l2-cache-controller";
- reg = <0xc20000 0x1000>;
- next-level-cache = <&cpc>;
- };
};
--
1.9.1
--
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