linux-kernel - Re: [PATCH 2/5] clk: berlin: add common clk driver for newer SoCs

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Date:	Thu, 1 Oct 2015 15:38:36 -0700
From:	Stephen Boyd <sboyd@...eaurora.org>
To:	Jisheng Zhang <jszhang@...vell.com>
Cc:	sebastian.hesselbarth@...il.com, catalin.marinas@....com,
	will.deacon@....com, mark.rutland@....com, robh+dt@...nel.org,
	pawel.moll@....com, ijc+devicetree@...lion.org.uk,
	galak@...eaurora.org, devicetree@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org, linux-clk@...r.kernel.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/5] clk: berlin: add common clk driver for newer SoCs

On 09/22, Jisheng Zhang wrote:
> +
> +static u8 clk_div[] = {1, 2, 4, 6, 8, 12, 1, 1};
> +
> +static unsigned long berlin_clk_recalc_rate(struct clk_hw *hw,
> +					unsigned long parent_rate)
> +{
> +	u32 val, divider;
> +	struct berlin_clk *clk = to_berlin_clk(hw);
> +
> +	val = readl_relaxed(clk->base);
> +	if (val & CLKD3SWITCH)
> +		divider = 3;
> +	else {
> +		if (val & CLKSWITCH) {
> +			val >>= CLKSEL_SHIFT;
> +			val &= CLKSEL_MASK;
> +			divider = clk_div[val];
> +		} else
> +			divider = 1;
> +	}

How about we drop the clk_div array and use code?

		if (val & CLKSWITCH) {
			val >>= CLKSEL_SHIFT;
			val &= CLKSEL_MASK;
		}

		divider = 1
		if (val < 6)
			divider <<= val;

> +
> +	return parent_rate / divider;
> +}

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