linux-kernel - Re: [PATCH v2 01/25] powerpc/8xx: Save r3 all the time in DTLB miss handler

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Date:	Tue, 6 Oct 2015 15:38:50 -0500
From:	Scott Wood <scottwood@...escale.com>
To:	christophe leroy <christophe.leroy@....fr>
CC:	Benjamin Herrenschmidt <benh@...nel.crashing.org>,
	Paul Mackerras <paulus@...ba.org>,
	Michael Ellerman <mpe@...erman.id.au>,
	<linux-kernel@...r.kernel.org>, <linuxppc-dev@...ts.ozlabs.org>
Subject: Re: [PATCH v2 01/25] powerpc/8xx: Save r3 all the time in DTLB miss
 handler

On Tue, 2015-10-06 at 22:30 +0200, christophe leroy wrote:
> Le 06/10/2015 18:46, Scott Wood a écrit :
> > On Tue, 2015-10-06 at 15:35 +0200, Christophe Leroy wrote:
> > > Le 29/09/2015 00:07, Scott Wood a écrit :
> > > > On Tue, Sep 22, 2015 at 06:50:29PM +0200, Christophe Leroy wrote:
> > > > > We are spending between 40 and 160 cycles with a mean of 65 cycles 
> > > > > in
> > > > > the TLB handling routines (measured with mftbl) so make it more
> > > > > simple althought it adds one instruction.
> > > > > 
> > > > > Signed-off-by: Christophe Leroy <christophe.leroy@....fr>
> > > > Does this just make it simpler or does it make it faster?  What is the
> > > > performance impact?  Is the performance impact seen with or without
> > > > CONFIG_8xx_CPU6 enabled?  Without it, it looks like you're adding an
> > > > mtspr/mfspr combo in order to replace one mfspr.
> > > > 
> > > > 
> > > The performance impact is not noticeable. Theoritically it adds 1 cycle
> > > on a mean of 65 cycles, that is 1.5%. Even in the worst case where we
> > > spend around 10% of the time in TLB handling exceptions, that represents
> > > only 0.15% of the total CPU time. So that's almost nothing.
> > > Behind the fact to get in simpler, the main reason is because I need a
> > > third register for the following patch in the set, otherwise I would
> > > spend a more time saving and restoring CR several times.
> > FWIW, the added instruction is an SPR access and I doubt that's only one
> > cycle.
> > 
> > 
> According to the mpc885 reference manual (table 9-1), Instruction 
> Execution Timing for "Move to: mtspr, mtcrf, mtmsr, mcrxr except mtspr to LR
> and CTR and to SPRs external to the core" is "serialize + 1 cycle".
> Taking into account we preeceeding instructions are also 'mtspr', we are 
> already serialized, so it is only one cycle I believe.
> Am I interpreting it wrong ?

I don't know.  The manual doesn't go into much detail about the mechanics of 
serialization.  If it's just about "block[ing] all execution units" without 
any effect on fetching, decoding, etc. then maybe you're right.

-Scott

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