linux-kernel - Re: [PATCH V2 1/2] x86/mcheck: Add Scalable MCA cpuid bit

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Date:	Fri, 30 Oct 2015 11:26:47 +0100
From:	Borislav Petkov <bp@...en8.de>
To:	Aravind Gopalakrishnan <Aravind.Gopalakrishnan@....com>
Cc:	tglx@...utronix.de, mingo@...hat.com, hpa@...or.com,
	tony.luck@...el.com, x86@...nel.org, ashok.raj@...el.com,
	linux-kernel@...r.kernel.org, linux-edac@...r.kernel.org,
	peterz@...radead.org, luto@...nel.org, dvlasenk@...hat.com,
	ross.zwisler@...ux.intel.com, dirk.j.brandewie@...el.com
Subject: Re: [PATCH V2 1/2] x86/mcheck: Add Scalable MCA cpuid bit

On Wed, Oct 28, 2015 at 02:03:29PM -0500, Aravind Gopalakrishnan wrote:
> Scalable MCA (SMCA) is a new feature in AMD Fam17h
> processors which indicates presence of MCA extensions.
> 
> MCA extensions expands existing register space for the
> MCE banks and also introduces a new MSR range to
> accommodate new banks. Future additions to AMD MCE code
> will first need to detect if SMCA is enabled before
> enabling the new features.
> 
> Adding code to detect if it SMCA is enabled in this patch
> and store that info in mce_vendor_flags structure.
> 
> Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@....com>
> ---
>  arch/x86/include/asm/mce.h       | 13 ++++++++++++-
>  arch/x86/kernel/cpu/mcheck/mce.c |  2 ++
>  2 files changed, 14 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
> index 2dbc0bf..63307b5 100644
> --- a/arch/x86/include/asm/mce.h
> +++ b/arch/x86/include/asm/mce.h
> @@ -135,7 +135,18 @@ struct mce_vendor_flags {
>  			 * in HW and deferred error interrupts.
>  			 */
>  			succor		: 1,
> -			__reserved_0	: 62;
> +
> +			/*
> +			 * Scalable MCA: This bit indicates support for MCAX
> +			 * (MCA EXtensions) which expands the register space

I changed that to SMCA. Let's refer to this feature with only one
abbreviation please. It seems hw vendors won't settle on names easily so
we should avoid that confusion in the kernel, at least.

Anyway, applied,
thanks.

-- 
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.
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