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Date:	Thu, 12 Nov 2015 08:35:18 -0500
From:	Peter Hurley <peter@...leysoftware.com>
To:	"Matwey V. Kornilov" <matwey@....msu.ru>
Cc:	Greg KH <gregkh@...uxfoundation.org>, jslaby@...e.com,
	linux-serial@...r.kernel.org,
	linux-kernel <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 3/3] tty: Add software emulated RS485 support for 8250

On 11/12/2015 07:34 AM, Matwey V. Kornilov wrote:
> 2015-11-10 19:12 GMT+03:00 Peter Hurley <peter@...leysoftware.com>:
>> On 11/07/2015 05:09 AM, Matwey V. Kornilov wrote:
>>> Implementation of software emulation of RS485 direction handling is based
>>> on omap-serial driver.  It is acts as the following. At transmission start,
>>> RTS is set (if required) and receiver is off (if required). At transmission
>>> stop, RTS is set (if required) and fifo is flushed.
>>>
>>> Signed-off-by: Matwey V. Kornilov <matwey@....msu.ru>
>>> ---
>>>  drivers/tty/serial/8250/8250_port.c | 32 ++++++++++++++++++++++++++++++++
>>>  1 file changed, 32 insertions(+)
>>>
>>> diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c
>>> index 52d82d2..a9291f7 100644
>>> --- a/drivers/tty/serial/8250/8250_port.c
>>> +++ b/drivers/tty/serial/8250/8250_port.c
>>> @@ -559,7 +559,37 @@ static void serial8250_rpm_put_tx(struct uart_8250_port *p)
>>>       pm_runtime_mark_last_busy(p->port.dev);
>>>       pm_runtime_put_autosuspend(p->port.dev);
>>>  }
>>> +static void serial8250_stop_rx(struct uart_port *port);
>>> +static void serial8250_rs485_start_tx(struct uart_8250_port *p)
>>> +{
>>> +     if (p->capabilities & UART_CAP_HW485 || !(p->port.rs485.flags & SER_RS485_ENABLED))
>>> +             return;
>>> +
>>> +     if (p->port.rs485.flags & SER_RS485_RTS_ON_SEND) {
>>> +             serial_port_out(&p->port, UART_MCR, UART_MCR_RTS);
>>
>> The SER_RS485_RTS_ON_SEND bit is supposed to be the logic level of RTS,
>> so RTS should be driven to either 0 or 1 here (not just to 1).
> 
> By the way, I've found that p->mcr caches MCR inconsistently. Is it
> supposed to be so? Or p->mcr is not for caching?

Not for caching; it's for modal settings (eg., AFE) that the 8250 port
driver needs to merge in when changing mctrl bits (DTR/RTS/etc).

The serial core caches the mctrl bits in uart_port->mctrl, but IMO
it would be simpler to always set/clear RTS here (rather than like
the omap-serial driver where it checks the gpio value first).

Is the assumption that userspace will not perform conflicting
operations, such as ioctl(TIOCMSET) or ioctl(TCSETSx), with RS485 enabled?

Regards,
Peter Hurley
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