linux-kernel - Re: [PATCH 4/4] Documentation: usb: dwc3: qcom: Add TCSR mux usage

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Date:	Fri, 20 Nov 2015 09:08:46 -0600
From:	Felipe Balbi <balbi@...com>
To:	Andy Gross <agross@...eaurora.org>, <linux-arm-msm@...r.kernel.org>
CC:	<linux-kernel@...r.kernel.org>,
	<linux-arm-kernel@...ts.infradead.org>,
	<linux-usb@...r.kernel.org>, Greg KH <gregkh@...uxfoundation.org>,
	<devicetree@...r.kernel.org>,
	Kishon Vijay Abraham I <kishon@...com>,
	Andy Gross <agross@...eaurora.org>
Subject: Re: [PATCH 4/4] Documentation: usb: dwc3: qcom: Add TCSR mux usage


Hi,

Andy Gross <agross@...eaurora.org> writes:
> This patch adds documentation for the optional syscon-tcsr property in the
> Qualcomm DWC3 node.  The syscon-tcsr specifies the register and bit used to
> configure the TCSR USB phy mux register.
>
> Signed-off-by: Andy Gross <agross@...eaurora.org>
> ---
>  Documentation/devicetree/bindings/usb/qcom,dwc3.txt | 11 +++++++++++
>  1 file changed, 11 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
> index ca164e7..dfa222d 100644
> --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
> +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
> @@ -8,6 +8,10 @@ Required properties:
>    "core"		Master/Core clock, have to be >= 125 MHz for SS
>  				operation and >= 60MHz for HS operation
>  
> +Optional properties:
> +- syscon-tcsr	Specifies TCSR handle, register offset, and bit position for
> +			configuring the phy mux setting.

oh, it's a PHY mux ? I don't think it should be part of any dwc3-* glue
layer then. By the time we reach dwc3, the mux should be properly
configured.

Kishon, any ideas ?

-- 
balbi

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