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Date: Fri, 20 Nov 2015 15:11:04 +0000 From: Jon Hunter <jonathanh@...dia.com> To: Peter De Schrijver <pdeschrijver@...dia.com>, Prashant Gaikwad <pgaikwad@...dia.com>, Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...eaurora.org>, Stephen Warren <swarren@...dotorg.org>, Thierry Reding <thierry.reding@...il.com>, Alexandre Courbot <gnurou@...il.com> CC: linux-clk@...r.kernel.org, linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org, Rhyland Klein <rklein@...dia.com>, Jon Hunter <jonathanh@...dia.com> Subject: [PATCH] clk: tegra: Fix bypassing of PLLs The _clk_disable_pll() function will attempt to place a PLL into bypass if the TEGRA_PLL_BYPASS is specified for the PLL and then disable the PLL by clearing the enable bit. To place the PLL into bypass, the bypass bit needs to be set and not cleared. Fix this by setting the bypass bit and not clearing it. Signed-off-by: Jon Hunter <jonathanh@...dia.com> --- drivers/clk/tegra/clk-pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index d6d4ecb88e94..e5aa9c87df4c 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -312,7 +312,7 @@ static void _clk_pll_disable(struct clk_hw *hw) val = pll_readl_base(pll); if (pll->params->flags & TEGRA_PLL_BYPASS) - val &= ~PLL_BASE_BYPASS; + val |= PLL_BASE_BYPASS; val &= ~PLL_BASE_ENABLE; pll_writel_base(val, pll); -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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