linux-kernel - [PATCH 2/6] QE: Add ucc hdlc document to bindings

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Date:	Fri, 8 Jan 2016 10:18:10 +0800
From:	Zhao Qiang <qiang.zhao@....com>
To:	<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
	<linuxppc-dev@...ts.ozlabs.org>
CC:	<Priyanka.Jain@...escale.com>, <oss@...error.net>,
	Zhao Qiang <qiang.zhao@....com>
Subject: [PATCH 2/6] QE: Add ucc hdlc document to bindings

Add ucc hdlc document to
Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/network.txt

Signed-off-by: Zhao Qiang <qiang.zhao@....com>
---
 .../bindings/powerpc/fsl/cpm_qe/network.txt        | 35 ++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/network.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/network.txt
index 29b28b8..017cbf7 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/network.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/network.txt
@@ -41,3 +41,38 @@ Example:
 		fsl,mdio-pin = <12>;
 		fsl,mdc-pin = <13>;
 	};
+
+* HDLC
+
+Currently defined compatibles:
+- fsl,ucc_hdlc
+
+Properties for fsl,ucc_hdlc:
+rx-clock-name : which clock QE use for RX
+tx-clock-name : which clock QE use for TX
+fsl,rx-sync-clock : which pin QE use for RX sync
+fsl,tx-sync-clock : which pin QE use for TX sync
+fsl,tx-timeslot : tx timeslot
+fsl,rx-timeslot : rx timeslot
+fsl,tdm-framer-type : tdm framer type
+fsl,tdm-mode : tdm mode, normal or internal-loopback
+fsl,tdm-id : tdm ID
+fsl,siram-entry-id : SI RAM entry ID for the TDM
+fsl,tdm-interface : hdlc based on tdm-interface
+
+Example:
+
+	ucc@...0 {
+		compatible = "fsl,ucc_hdlc";
+		rx-clock-name = "clk8";
+		tx-clock-name = "clk9";
+		fsl,rx-sync-clock = "rsync_pin";
+		fsl,tx-sync-clock = "tsync_pin";
+		fsl,tx-timeslot = <0xfffffffe>;
+		fsl,rx-timeslot = <0xfffffffe>;
+		fsl,tdm-framer-type = "e1";
+		fsl,tdm-mode = "normal";
+		fsl,tdm-id = <0>;
+		fsl,siram-entry-id = <0>;
+		fsl,tdm-interface;
+	};
-- 
2.1.0.27.g96db324