linux-kernel - Re: [PATCH RFC 1/1] ASoC: fsl_ssi: Make fifo watermark and maxburst settings device tree options

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Date:	Fri, 15 Jan 2016 10:12:49 -0800
From:	Nicolin Chen <nicoleotsuka@...il.com>
To:	Caleb Crome <caleb@...me.org>
Cc:	Timur Tabi <timur@...i.org>, Xiubo Li <Xiubo.Lee@...il.com>,
	Liam Girdwood <lgirdwood@...il.com>,
	Mark Brown <broonie@...nel.org>,
	Jaroslav Kysela <perex@...ex.cz>,
	Takashi Iwai <tiwai@...e.com>, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	"alsa-devel@...a-project.org" <alsa-devel@...a-project.org>
Subject: Re: [PATCH RFC 1/1] ASoC: fsl_ssi: Make fifo watermark and maxburst
 settings device tree options

On Thu, Jan 14, 2016 at 08:56:31PM -0800, Caleb Crome wrote:
> On Thu, Jan 14, 2016 at 6:45 PM, Nicolin Chen <nicoleotsuka@...il.com> wrote:
> > On Thu, Jan 14, 2016 at 01:26:24PM -0800, Caleb Crome wrote:
> >
> >> As for optimal settings, I finally came to a setting of 4 for depth &
> >> maxburst, which will result in more DMA requests, but it's the only
> >> way that works at 48kHz for me.  The default settings is 13 (15 - 2)
> >> for the ones of the 15 item fifo, which is a pretty dramatic
> >> difference.  I just don't know if other chips will behave badly in
> >> that case.
> >
> > What's your final configuration for TFWM0 bits, 4?
> 
> Yes, a value of 4 for my use case:  i.MX6 @ 768000 words/second (48khz
> * 16 channels).

4 means there are >= 4 empty slots in the FIFO, so there are no more
than 11 remaining data. This makes sense.

IIRC, the Freescale official BSP release for i.MX is used to set 6 to
TFWM0/1 in the old day, not sure about recent ones though. So I think
setting 4 to TFWM0/1 should work for most of cases. We may also let
others test it before merging it.

Actually a setting of 13 is much more risky in my opinion. It means
only two empty slots in the FIFO, so it might be easily to get under/
overflow if a DMA transaction gets delay somehow. The only benefit is
that DMA requests and interrupt (FIQ) can be reduced.