linux-kernel - [PATCH 4.4 64/74] cxl: Fix PSL timebase synchronization detection

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Date:	Mon,  7 Mar 2016 16:03:29 -0800
From:	Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To:	linux-kernel@...r.kernel.org
Cc:	Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
	stable@...r.kernel.org,
	Frederic Barrat <fbarrat@...ux.vnet.ibm.com>,
	Michael Neuling <mikey@...ling.org>,
	"Matthew R. Ochs" <mrochs@...ux.vnet.ibm.com>,
	Ian Munsie <imunsie@....ibm.com>,
	Andrew Donnellan <andrew.donnellan@....ibm.com>,
	Vaibhav Jain <vaibhav@...ux.vnet.ibm.com>,
	Michael Ellerman <mpe@...erman.id.au>
Subject: [PATCH 4.4 64/74] cxl: Fix PSL timebase synchronization detection

4.4-stable review patch.  If anyone has any objections, please let me know.

------------------

From: Frederic Barrat <fbarrat@...ux.vnet.ibm.com>

commit 923adb1646d5ba739d2a1e63ee20d60574d9da8e upstream.

The PSL timebase synchronization is seemingly failing for
configuration not including VIRT_CPU_ACCOUNTING_NATIVE. The driver
shows the following trace in dmesg:
PSL: Timebase sync: giving up!

The PSL timebase register is actually syncing correctly, but the cxl
driver is not detecting it. Fix is to use the proper timebase-to-time
conversion.

Signed-off-by: Frederic Barrat <fbarrat@...ux.vnet.ibm.com>
Acked-by: Michael Neuling <mikey@...ling.org>
Reviewed-by: Matthew R. Ochs <mrochs@...ux.vnet.ibm.com>
Acked-by: Ian Munsie <imunsie@....ibm.com>
Reviewed-by: Andrew Donnellan <andrew.donnellan@....ibm.com>
Reviewed-by: Vaibhav Jain <vaibhav@...ux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@...erman.id.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@...uxfoundation.org>

---
 drivers/misc/cxl/pci.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- a/drivers/misc/cxl/pci.c
+++ b/drivers/misc/cxl/pci.c
@@ -414,7 +414,7 @@ static int cxl_setup_psl_timebase(struct
 		delta = mftb() - psl_tb;
 		if (delta < 0)
 			delta = -delta;
-	} while (cputime_to_usecs(delta) > 16);
+	} while (tb_to_ns(delta) > 16000);

 	return 0;
 }