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Date:	Sat, 19 Mar 2016 08:44:09 +0100
From:	Martin Sperl <kernel@...tin.sperl.org>
To:	Eric Anholt <eric@...olt.net>
Cc:	Stefan Wahren <stefan.wahren@...e.com>,
	John Youn <John.Youn@...opsys.com>,
	Doug Anderson <dianders@...omium.org>,
	Michael Niewoehner <linux@...ewoehner.de>,
	Tao Huang <huangtao@...k-chips.com>,
	Julius Werner <jwerner@...omium.org>,
	Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-usb@...r.kernel.org" <linux-usb@...r.kernel.org>,
	Caesar Wang <caesar.upstream@...il.com>,
	Heiko Stuebner <heiko@...ech.de>,
	Felipe Balbi <balbi@...nel.org>,
	Remi Pommarel <repk@...plefau.lt>
Subject: Re: [RFT PATCH 2/2] Revert "usb: dwc2: Fix probe problem on bcm2835"


> On 19.03.2016, at 03:17, Eric Anholt <eric@...olt.net> wrote:
> 
> Stefan Wahren <stefan.wahren@...e.com> writes:
> 
>> Hi Eric,
>> hi Martin,
>> 
>>> John Youn <John.Youn@...opsys.com> hat am 16. März 2016 um 19:28 geschrieben:
>>> 
>>> 
>>> On 3/10/2016 11:14 AM, John Youn wrote:
>>>> On 3/9/2016 11:06 AM, Doug Anderson wrote:
>>>>> 
>>>>> John: it's pretty clear that there's something taking almost exactly
>>>>> 10ms on my system and almost exactly 50ms on Stefan's system. Is
>>>>> there some register we could poll to see when this process is done?
>>>>> ...or can we look at the dwc2 revision number / feature register and
>>>>> detect how long to delay?
>>>>> 

Maybe this difference is related to overclocking settings in the firmware?

>>> 
>>> 1. What is the AHB Clock frequency? Is the AHB Clock gated during
>>> Reset?
> 
> Low confidence here as I'm tracing lines across a ton of modules, but it
> looks like it comes from the USB AXI clock in peri_image, which is a
> gate on the normal 250Mhz APB clock, but nothing should be touching that
> gate register as part of USB reset as far as I know.
> 
Isn’t it possible that this clock (probably BCM2835_CLOCK_VPU) is 
changed by the firmware due to overclocking settings in /boot/config.txt?

Martin


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