lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:	Fri, 25 Mar 2016 14:31:12 -0700
From:	Bjorn Andersson <bjorn.andersson@...aro.org>
To:	Matthew McClintock <mmcclint@...eaurora.org>,
	linus.walleij@...aro.org
Cc:	andy.gross@...aro.org, linux-arm-msm@...r.kernel.org,
	qca-upstream.external@....qualcomm.com,
	Sricharan R <sricharan@...eaurora.org>,
	Rob Herring <robh@...nel.org>,
	Mathieu Olivari <mathieu@...eaurora.org>,
	Varadarajan Narayanan <varada@...eaurora.org>,
	"open list:PIN CONTROL SUBSYSTEM" <linux-gpio@...r.kernel.org>,
	open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 03/17] pinctrl: qcom: ipq4019: fix register offsets

On Wed 23 Mar 15:04 PDT 2016, Matthew McClintock wrote:

> For this SoC the register offsets changed from previous versions to be
> separated by a larger amount.
> 
> CC: linus.walleij@...aro.org

So the HW guys changed the register layout of the TLMM block? Matches
the layout of contemporary MSMs, so I see no problems with this.

Acked-by: bjorn.andersson@...aro.org

Regards,
Bjorn

> Signed-off-by: Matthew McClintock <mmcclint@...eaurora.org>
> ---
>  drivers/pinctrl/qcom/pinctrl-ipq4019.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
> index cb9f16a..b68ae42 100644
> --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
> +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
> @@ -254,11 +254,11 @@ DECLARE_QCA_GPIO_PINS(99);
>  			qca_mux_##f14			\
>  		},				        \
>  		.nfuncs = 15,				\
> -		.ctl_reg = 0x1000 + 0x10 * id,		\
> -		.io_reg = 0x1004 + 0x10 * id,		\
> -		.intr_cfg_reg = 0x1008 + 0x10 * id,	\
> -		.intr_status_reg = 0x100c + 0x10 * id,	\
> -		.intr_target_reg = 0x400 + 0x4 * id,	\
> +		.ctl_reg = 0x0 + 0x1000 * id,		\
> +		.io_reg = 0x4 + 0x1000 * id,		\
> +		.intr_cfg_reg = 0x8 + 0x1000 * id,	\
> +		.intr_status_reg = 0xc + 0x1000 * id,	\
> +		.intr_target_reg = 0x8 + 0x1000 * id,	\
>  		.mux_bit = 2,			\
>  		.pull_bit = 0,			\
>  		.drv_bit = 6,			\
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ