lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Date:	Sat, 26 Mar 2016 05:13:46 -0700
From:	Srinivas Pandruvada <srinivas.pandruvada@...ux.intel.com>
To:	"Rafael J. Wysocki" <rafael@...nel.org>
Cc:	"Rafael J. Wysocki" <rjw@...ysocki.net>,
	Tony Luck <tony.luck@...el.com>,
	Borislav Petkov <bp@...en8.de>,
	Thomas Gleixner <tglx@...utronix.de>,
	Ingo Molnar <mingo@...hat.com>,
	"H. Peter Anvin" <hpa@...or.com>, Len Brown <lenb@...nel.org>,
	"open list:EDAC-CORE" <linux-edac@...r.kernel.org>,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	ACPI Devel Maling List <linux-acpi@...r.kernel.org>
Subject: Re: [PATCH v7] acpi: Issue _OSC call for native thermal interrupt
 handling

On Sat, 2016-03-26 at 01:56 +0100, Rafael J. Wysocki wrote:
> On Thu, Mar 24, 2016 at 5:07 AM, Srinivas Pandruvada
> <srinivas.pandruvada@...ux.intel.com> wrote:
> > There are several reports of freeze on enabling HWP (Hardware
> > PStates)
> > feature on Skylake based systems by Intel P states driver. The root
> > cause is identified as the HWP interrupts causing BIOS code to
> > freeze.
> > HWP interrupts uses thermal LVT.
> > Linux natively handles thermal interrupts, but in Skylake based
> > systems
> > SMM will take control of thermal interrupts. This is a problem for
> > several
> > reasons:
> > - It is freezing in BIOS when tries to handle thermal interrupt,
> > which
> > will require BIOS upgrade
> > - With SMM handling thermal we loose all the reporting features of
> > Linux arch/x86/kernel/cpu/mcheck/therm_throt driver
> > - Some thermal drivers like x86-package-temp driver depends on the
> > thermal
> > threshold interrupts
> > - The HWP interrupts are useful for debugging and tuning
> > performance
> > 
> > So we need native handling of thermal interrupts. This requires
> > some
> > way to inform SMM that OS can handle thermal interrupts. This can
> > be
> > done by using _OSC/_PDC under processor scope very early in ACPI
> > initialization flow.
> > The bit 12 of _OSC/_PDC in processor scope defines whether OS
> > supports
> > handling of native interrupts for Collaborative Processor
> > Performance
> > Control (CPPC) notifications. Since HWP is a implementation of
> > CPPC,
> > setting this bit is equivalent to inform SMM that OS is capable of
> > handling thermal interrupts.
> > Refer to this document for details on _OSC/_PDC
> > http://www.intel.com/content/www/us/en/standards/processor-vendor-
> > specific-acpi-specification.html
> > 
> > This change introduces a new function
> > acpi_early_processor_set_osc(),
> > which walks acpi name space and finds acpi processor object and
> > set capability via _OSC method.
> > 
> > Also this change writes HWP status bits to 0 to clear any HWP
> > status
> > bits in intel_thermal_interrupt().
> > 
> > Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@...ux.intel
> > .com>
> 
> I've queued it up, but I have modified the subject and the changelog
> and renamed the new function.
> 
> Please have a look at
> http://git.kernel.org/cgit/linux/kernel/git/rafael/linux-pm.git/commi
> t/?h=bleeding-edge&id=42341f87ba1bee4c5be95038c24abb69cbcf361a
> and let me know if it makes sense to you.

Looks fine to me.

Thanks,
Srinivas

> 
> Thanks,
> Rafael

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ